• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.3
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• pp.137-140
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• 2014

With the recent advent of through silicon via (TSV) technology, wafer level-TSV interconnection become feasible in high volume manufacturing. To increase the manufacturing productivity, it is required to develop equipment for backside passivation layer deposition for TSV wafer bonding process with high deposition rate and low film stress. In this research, we investigated the relationship between process parameters and the induced wafer stress of PECVD silicon nitride film on 300 mm wafers employing statistical and artificial intelligence modeling. We found that the film stress increases with increased RF power, but the pressure has inversely proportional to the stress. It is also observed that no significant stress change is observed when the gas flow rate is low.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.793-796
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• 2005

In this paper, we propose a method which can improve uniformity of a miniaturized electron beam array for inspection of very small pattern with high speed using vertical interconnection. This method enables the individual control of columns so that it can reduce the deviation of beam current, beam size, scan range and so on. The test device that used vertical interconnection method was fabricated by multiple wafer bonding and metal reflow. Two silicon and one glass wafers were bonded and metal interconnection by melting of electroplated AuSn was performed. The contact resistance was under $10{\Omega}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.3
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• pp.133-139
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• 2007

Future MEMS systems will be composed of larger varieties of devices with very different functionality such as electronics, mechanics, optics and bio-chemistry. Integration technology of heterogeneous devices must be developed. This article first deals with the current development trend of new fabrication technologies; those include self-assembling of parts over a large area, wafer-scale encapsulation by wafer-bonding, nano imprinting, and roll-to-roll printing. In the latter half of the article, the concept towards the heterogeneous integration of devices and functionality into micro/nano systems is described. The key idea is to combine the conventional top-down technologies and the novel bottom-up technologies for building nano systems. A simple example is the carbon nano tube interconnection that is grown in the via-hole of a VLSI chip. In the laboratory level, the position-specific self-assembly of nano parts on a DNA template was demonstrated through hybridization of probe DNA segments attached to the parts. Also, bio molecular motors were incorporated in a micro fluidic system and utilized as a nano actuator for transporting objects in the channel.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.29-36
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• 2008

In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of $1mm{\times}1mm{\times}700{\mu}m$. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.

• Transactions of the Society of Information Storage Systems
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• v.2 no.3
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• pp.163-168
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• 2006

Small form factor optical pickup (SFFOP) corresponding to BD specifications is strongly proposed for the next-generation portable storage device. In order to generate SFFOP, small sized optical pickup has been fabricated. We have developed a small sited optical pickup that is called the integrated optical pickup (IOP). The fabrication method of this system is mainly dependant on the use of the wafer based micro fabrication technology, which has been used in MEMS process such as photolithography, reactive ion etching, wafer bonding, and packaging process. This approach has the merits for mass production and high assembling accuracy. In this study, to generate the small sized optical pickup for high recording capacity, IOP corresponding to BD specifications has been designed and developed, including three main parts, 1) design, fabrication and evaluation of objective lens unit, 2) design and fabrication of IOP and 3) evaluation process of FES and TES.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.75-81
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• 2018

The effect of $Ar-N_2$ plasma treatment on Cu surface as one of solutions to realize reliable Cu-Cu wafer bonding was investigated. Structural characteristic of $Ar-N_2$ plasma treated Cu surface were analyzed using X-ray diffraction, X-ray photoelectron spectroscopy, atomic force microscope. Ar gas was used for a plasma ignition and to activate Cu surface by ion bombardment, and $N_2$ gas was used to protect the Cu surface from contamination such as -O or -OH by forming a passivation layer. The Cu specimen under high Ar partial pressure plasma treatment showed more copper oxide due to the activation on Cu surface, while Cu surface after high $N_2$ gas partial pressure plasma treatment showed less copper oxide due to the formation of Cu-N or Cu-O-N passivation layer. It was confirmed that nitrogen plasma can prohibit Cu-O formation on Cu surface, but nitrogen partial pressure in the $Ar-N_2$ plasma should be optimized for the formation of nitrogen passivation layer on the entire surface of Cu wafer.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.11-15
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• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.326-331
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• 2014

In this study, a MEMS microphone that uses $Si_3N_4$ as the vibration membrane was produced for application as an auditory device using a sound visualization technique (sound visualization) for the hearing impaired. Two sheets of 6-inch silicon wafer were each fabricated into a vibration membrane and back plate, after which, wafer bonding was performed. A certain amount of charge was created between the bonded vibration membrane and the back plate electrodes, and a MEMS microphone that functioned through the capacitive method that uses change in such charge was fabricated. In order to evaluate the characteristics of the prepared MEMS microphone, the frequency flatness, frequency response, properties of phase between samples, and directivity according to the direction of sound source were analyzed. The MEMS microphone showed excellent flatness per frequency in the audio frequency (100 Hz-10 kHz) and a high response of at least -42 dB (sound pressure level). Further, a stable differential phase between the samples of within -3 dB was observed between 100 Hz-6 kHz. In particular, excellent omnidirectional properties were demonstrated in the frequency range of 125 Hz-4 kHz.

• Transactions on Electrical and Electronic Materials
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• v.14 no.2
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• pp.63-66
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• 2013

This paper describes the highly productive process technologies of microprobe arrays, which were used for a probe card to test a Dynamic Random Access Memory (DRAM) chip with fine pitch pads. Cantilever-type microprobe arrays were fabricated using conventional micro-electro-mechanical system (MEMS) process technologies. Bonding material, gold-tin (Au-Sn) paste, was used to bond the Ni-Co alloy microprobes to the ceramic space transformer. The electrical and mechanical characteristics of a probe card with fabricated microprobes were measured by a conventional probe card tester. A probe card assembled with the fabricated microprobes showed good x-y alignment and planarity errors within ${\pm}5{\mu}m$ and ${\pm}10{\mu}m$, respectively. In addition, the average leakage current and contact resistance were approximately 1.04 nA and 0.054 ohm, respectively. The proposed highly productive microprobes can be applied to a MEMS probe card, to test a DRAM chip with fine pitch pads.