• Journal of information and communication convergence engineering
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• 제7권2호
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• pp.215-218
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• 2009

In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.

• 전기학회논문지
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• 제67권5호
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• pp.611-616
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• 2018

In the cost based pool market in Korea, there is no compensation of reactive power because the fuel cost for reactive power is relatively low compared to that of active power. However, the change of energy paradigm in the future, such as widespread integration of distributed renewable energy source, will prevent the system operator from mandating the reactive power supply without any compensation. Thus, in this study, we propose the reference voltage of the 345 kV transmission system that minimizes the reactive power supply. This is closely related to the economic dispatch of reactive power aiming at minimizing the compensation cost for the reactive power service. In order to verify the effectiveness of the proposed reference voltage, the simulations are performed using the IEEE 14 bus system and the KEPCO real networks. The simulation results show that a voltage lower than the current reference value is recommended to reduce the reactive power supply and also suggest that the current voltage specification for the 345 kV system needs to be reviewed.

• 전력전자학회논문지
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• 제3권2호
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• pp.118-124
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• 1998

This paper describes a relationship of a space vector PWM and a sinusoidal PWM and presents that the space vector PWM can produce linearly the output voltage to the unity MI(modulation index). At first, reference angles and holding angles are derived from expanding a Fourier series of the reference voltage waveform and then the angles are used for the inverter switching to linearize transfer characteristics of the inverter. In addition, the harmonic components of the output voltage are analyzed and on-line control is shown to be feasible by approximating in piecewise-linearization the reference and holding angles versus the MI. In V/f control of the induction motor, it is verified by the experiment that the motor current is changed smoothly for the variation of the inverter input voltage and the change of the reference voltage.

• 전자공학회논문지C
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• 제34C권4호
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• pp.1-15
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• 1997

This paper proposes CMOS on-chip voltage and current reference circuits that operate at supply voltages between 2.5V and 5.5V without using a vonventional bandgap voltage structure. The proposed reference circuits based on enhancement-type MOS transistors show low cost, compatibility with other on-chip MOS circuits, low-power consumption, and small-chip size. The prototype was implemented in a 0.6 um n-well single-poly double-metal CMOS process and occupies an active die area of $710 um \times 190 um$. The proposed voltage reference realizes a mean value of 0.97 V with a standard deviation of $\pm0.39 mV$, and a temperature coefficient of $8.2 ppm/^{\circ}C$ over an extended temeprature range from TEX>$-25^{\circ}C$ to $75^{\circ}C$. A measured PSRR (power supply rejection ratio) is about -67 dB at 50kHz.

• 한국정보통신학회논문지
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• 제11권8호
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• pp.1552-1557
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• 2007

본 논문에서는 밴드갭 기준전압을 이용하여 동작온도에 무관한 PWM(Pulse Width Modulation) 제어 회로를 설계 하였다. 동작온도에 무관한 PWM 제어기는 BiCMOS 기술을 이용하여 동작온도에 무관한 기준전압과 동작온도에 따라 변화하는 두개의 기준 전압을 이용하였다. 설계되어진 회로는 공급전압 3.3volt를 사용하였으며, 출력 주파수는 1MHz이다. 회로의 시뮬레이션 결과 동작 온도가 $0^{\circ}C$에서 $70^{\circ}C$까지 변화할 때, PWM 제어기의 출력 펄스폭의 변화는 상온에 비하여 +0.86%에서 -0.38%였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 A
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• pp.265-267
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• 2000

A method to compute the reactive powers of the added buses by the decoupled UPFC model for the optimal voltage profile is presented, by which the voltage magnitudes of PQ buses can get closer to the reference value(usually one p.u.). The performance index for assessing how much the voltage magnitude is closer to the reference value is defined as the squared sum of the present voltage minus the reference voltage multiplied by the weighting number associated with the relative importance of the buses. Numerical example in a 10-unit 39-bus power system with 2 UPFC's shows that the performance index can be very much reduced by operating multi UPFC's with the reactive powers for the optimal voltage profile proposed in this paper.

• 전력전자학회논문지
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• 제8권5호
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• pp.442-449
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• 2003

본 논문은 PQR 순시전력 이론을 이용하여 순시전압보상장치 (DVR)에서 기준보상전압을 결정하는 방법을 제시한다. 측정된 3상 단자 전압은 시간지연 없이 PQR 좌표계로 변환된다. PQR 좌표계의 기준전압은 단일한 직류값이므로 DVR의 전압제어기는 단순하고 쉽게 설계가 가능해 진다. 제안된 제어방식은 피드백 제어기나 피드포워드 제어기에 모두 적용될 수 있다. 본 논문에서는 피드포워드 제어기에 대하여 이론을 적용하였으며 실험 및 시뮬레이션으로 검증을 하였다.

• 전력전자학회논문지
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• 제18권5호
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• pp.422-428
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• 2013

Recently, we use a static synchronous compensator(STATCOM) with cascaded H-bride topologies, because it is easy to increase capacity and to reduce total harmonic distortion(THD). When we use equipment for reactive power compensation, dc-link voltage unbalances occur from several reasons although loads are balanced. In the past, switching pattern change of single phase inverter and reference voltage magnitude change of inverter equipped with power sensor have been used for dc-link voltage balance. But previous methods are more complicated and expensive because of additional component costs. Therefore, this paper explains reasons of dc-link voltage unbalance and proposes solution. This solution is complex method that is composed of reference voltage magnitude change of inverter without additional hardware and shifted phase angle of inverter reference voltages change. It proves possibility through 1000[KVA] system simulation.

• 한국정보기술학회 영문논문지
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• 제8권2호
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• pp.59-67
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• 2018

The minimum power supply voltage of a typical bandgap current reference (BGCR) is limited by operating temperature and input common mode range (ICMR) of a feedback amplifier. A new BGCR using a bandgap voltage generator (BGVG) is proposed to minimize the effect of temperature, supply voltage, and process variation. The BGVG is designed with proportional to absolute temperature (PTAT) characteristic, and a feedback amplifier is designed with weak-inversion transistors for low voltage operation. It is verified with a $0.18-{\mu}m$ CMOS process with five corners for MOS transistors and three corners for BJTs. The proposed circuit is superior to other reported current references under temperature variation from $-40^{\circ}C$ to $120^{\circ}C$ and power supply variation from 1.2 V to 1.8 V. The total power consumption is $126{\mu}W$ under the conditions that the power supply voltage is 1.2 V, the output current is $10{\mu}A$, and the operating temperature is $20^{\circ}C$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.685-694
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• 2015

In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of $64{\times}64$, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of $128{\times}128$, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.