• 전기학회논문지
• /
• 제63권8호
• /
• pp.1046-1054
• /
• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• 전기학회논문지
• /
• 제63권12호
• /
• pp.1640-1648
• /
• 2014

This paper proposes a switching frequency reduction method for MMC (Modular Multilevel Converter) utilizing redundancy operation of sub-module, which can offer reduction of voltage harmonics and switching loss. The feasibility of proposed method was verified through computer simulations with PSCAD/EMTDC software. Based on simulation analysis, a hardware scaled-model of 10kVA, DC-1000V MMC was designed and manufactured in the lab. Various experiments were conducted to verify the feasibility of proposed method in the actual hardware system. The hardware scaled-model can be effectively utilized for analyzing the performance of MMC according to the modulation scheme and redundancy operation.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2000년도 전력전자학술대회 논문집
• /
• pp.313-316
• /
• 2000

This paper proposes a new solution by carrier-based SVPWM method to solve the most serious problem of Flying Capacitor Multi-level Inverter that is unbalance of capacitor voltages The voltage unbalance is occurred by the difference of each capacitor's charging and discharging time applied to Flying Capacitor Multi-level Inverter. It controls the variation of capacitor voltages into the mean'0' during some period by means of new carriers using the leg voltage redundancy in the Inverter. The solution can be easily expanded to the multi-level. Also this method can make the switching loss and conduction loss of device equal by the use of leg voltage redundancy. First the unbalance of capacitor voltage is analyzed and the conventional theory of self-balance using phase-shifted carrier is reviewed. And then the new method that is suitable to the Flying Capacitor Inverter is explained. The simulation results would be shown to verify the proposed method

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2014년도 전력전자학술대회 논문집
• /
• pp.209-210
• /
• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability.

• 전력전자학회논문지
• /
• 제7권1호
• /
• pp.65-73
• /
• 2002

본 논문에서는 플라잉 커패시터 멀티-레벨 인버터의 가장 큰 문제점인 커패시터 전압 불균형을 캐리어 비교방식을 토대로 한 펄스 폭 변조 방식(PWM)을 이용하여 제어하는 새로운 PWM방법을 제안한다. 제안된 방법은 멜티-레벨 인버터로 확장이 용이한 캐리어 비교 방식의 PWM방법으로서 플라잉 커패시터 인버터에서 소자의 스위칭시각 커패시터의 충·방전으로 인해 발생되는 전압불균형에 대해 상전압 리던던시와 선간전압 리던던시를 이용하여 커패시터 전압의 변화량을 일정주기에 대해 평균적으로 영으로 제어하게 된다. 또한 이 방법은 상전압 리던던시를 고르게 이용하여 소자의 스위치 손실과 도통 손실을 같게 하는 장점을 지닌다. 본문에서 플라잉 커패시터 인버터에 서 발생하는 커패시터 전압 불균형에 대해 분석하고 이 인버터에 적합한 캐리어 비교방식의 PWM방법을 설명한다.

• 한국전기전자재료학회논문지
• /
• 제13권4호
• /
• pp.273-279
• /
• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• 전력전자학회논문지
• /
• 제20권3호
• /
• pp.273-279
• /
• 2015

A zero vector selection method to reduce switching losses for model predictive control (MPC) of voltage source inverter is proposed. A conventional MPC of voltage source inverter has not been proposed, and a method to select the redundancy of the zero vector is required for this study. In this paper, the redundancy of the zero vectors is selected with generating a zero sequence voltage to reduce switching losses. The zero vector of 2-level inverter is determined by determining sign of the zero sequence voltage. In the proposed method, the quality of the current is retained and switching loss can be reduced compared with the conventional method. This result was verified by P-sim simulation and experiments.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
• /
• pp.625-629
• /
• 2004

This paper presents a systematical approach to study carrier based PWM techniques (CPWM) in diode-clamped and cascade multilevel inverters by using a proposed named multi-modulating pattern method. This method is based on the vector correlation between CPWM and the space vector PWM (SVPWM) and applicable to both multilevel inverter topologies. A CPWM technique can be described in a general mathematical equation, and obtain the same outputs similarly as of the corresponding SVPWM. Control of the fundamental voltage, vector redundancies and phase redundancies in multilevel inverter can be formulated separately in the CPWM equation. The deduced CPWM can obtain the full vector redundancy control, and fully utilize phase redundancy in a cascade inverter In this continued part, it will be deduced correlation between CPWM equations in multi-carrier system and single carrier system, present the mathematical model of voltage source inverter related to the common mode voltage and propose a general algorithm for multi-modulating modulator. The obtained theory will be demonstrated by simulation results.

• 한국정보통신학회논문지
• /
• 제14권8호
• /
• pp.1877-1886
• /
• 2010

본 논문에서는 전기적인 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로를 설계하였다. 공급전원이 낮아지더라도 외부 프로그램 전원을 사용하여 높은 프로그램 파워를 eFuse (electrical fuse)에 공급하면서 셀의 읽기 전류를 줄일 수 있는 듀얼 포트 eFuse 셀을 제안하였다. 그리고 제안된 듀얼 포트 eFuse 셀은 파워-온 읽기 기능으로 eFuse의 프로그램 정보가 D-래치에 자동적으로 저장되도록 설계하였다. 또한 메모리 리페어 주소와 메모리 액세스 주소를 비교하는 주소 비교 회로는 dynamic pseudo NMOS 로직으로 구현하여 기존의 CMOS 로직을 이용한 경우 보다 레이아웃 면적을 19% 정도 줄였다. 전기적인 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로는 동부하이텍 $0.11{\mu}m$ Mixed Signal 공정을 이용하여 설계되었으며, 레이아웃 면적은 $249.02{\times}225.04{\mu}m^{2}$이다.

• 전력전자학회논문지
• /
• 제8권6호
• /
• pp.469-477
• /
• 2003

본 논문은 플라잉 커패시터 멀티-레벨 인버터의 가장 큰 문제점인 플라잉 커패시터 전압 불균형의 새로운 해결방법으로 캐리어 로테이션(Carrier-Rotation) PWM 기법을 제안한다. 제안된 기법은 모든 스위치가 한번의 스위칭동작을 하는 동안 플라잉 커패시터의 충전과 방전에 관계된 레그 전압 리던던시(redundancy)를 같은 비율로 사용하여 플라잉 커패시터 전압을 일정하게 유지하며, 전압의 변동폭이 최소가 되도록 제어한다 이 방법은 각 캐리어의 배치가 모두 통상이므로 출력 전압의 고조파 성분이 저감되며, 또한 모든 스위치의 스위칭 주파수가 같으므로 스위치 이용률이 개선되는 특성을 갖는다. 제안된 기법을 플라잉 커패시터 3-레벨 인버터에 적용하여 상세히 분석하고, 3-레벨 이상에 적용할 수 있도록 일반화한다. 제안된 기법의 타당성은 실험 결과로 검증된다.