• Journal of Multimedia Information System
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• v.6 no.1
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• pp.7-14
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• 2019

This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.249-256
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• 2007

GPS(generalized processor sharing) is a fair scheduling scheme that guarantees fair distribution of resources in an instantaneous manner, while virtual clock pursues fairness in the sense of long-term. In this paper, we notice that the degree of memorylessness is the key difference of the two schemes, and propose a unified scheduling model that covers the whole spectrum of history-sensitiveness. In this model, each application's resource right is represented in a value called deposit, which is accumulated at a predefined rate and is consumed for services. The unused deposit, representing non-usage history, gives the application more opportunity to be scheduled, hence relatively enhancing its response time. Decay of the deposit means partial erase of the history and, by adjusting the decaying rate, the degree of history-sensitiveness is controlled. In the spectrum, the memoryless end corresponds GPS and the other end with full history corresponds virtual clock. And there exists a tradeoff between average delay and long-term fairness. We examine the properties of the model by analysis and simulation.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.543-556
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• 2009

Recently, NAND flash memory is being used as the swap device of virtual memory as well as the file storage of mobile systems. Since temporal locality is dominant in page references of virtual memory, LRU and its approximated CLOCK algorithms are widely used. However, cost of a write operation in flash memory is much larger than that of a read operation, and thus a page replacement algorithm should consider this factor. This paper analyzes virtual memory read/write reference patterns individually, and observes the ranking inversion problem of temporal locality in write references which is not observed in read references. With this observation, we present a new page replacement algorithm considering write frequency as well as temporal locality in estimating write reference behaviors. This new algorithm dynamically allocates memory space to read/write operations based on their reference patterns and I/O costs. Though the algorithm has no external parameter to tune, it supports optimized implementations for virtual memory systems, and also performs 20-66% better than CLOCK, CAR, and CFLRU algorithms.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.243-245
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• 1998

미래의 셀룰라 이동통신망은 멀티미디어 데이터 서빗를 제공하기 위해서 높은 대역폭이 필요하기 때문에 셀의 크기가 수십 미터 내오인 피코 실(pico cell)로 구성되는 피코 셀 망이 될 것이다. 이와 같은 피코 셀룰라 망에서는 이동통신자의 우치 변화에 따른 handoff 처리 회수가 상대적으로 증가하므로, handoff 처리로 인한 망부하가 늘어났고, handoff처리 지연으로 인하여 사용자는 중단없는 연결서비스 (seamless connection service)를 받지 못할 수도 있다. 본 논문은 VT-CSMA방식을 응용한 기법을 새로운 handoff방식으로 제안한다. 이 기법은 handoff에서 사용하고 delay time virtual clock 과 real clock 의 2개의 clock을 갖도록 함으로써, 빠른 속도로 이동하는 호는 느린 속도로 이동하는 호보다 상대적으로 짧은 시간 내에 handoff가 처리 되도록 한다. 모의 실험 결과는 VT-CSMA기법을 응용한 새로운 방식이 기존 CDMA 방식에서 drop되는 호를 많이 줄이는 효과가 있음을 보인다.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.11a
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• pp.335-342
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• 2000

멀티미디어 정보를 처리하기 위해서 필수적으로 필요한 기술이 멀티미디어 동기화를 구성하는 것이다. 본 논문에서는 두 시스템 사이의 클럭 동기를 맞추어 주기 위하여 가상 클럭(VGC : Virtual Global Clock)을 제안하였다. Loop flack 방법에 의한 제안된 가상 클럭은 통신이 가능한 모든 환경에 적용할 수 있다

• Proceedings of the Korean Information Science Society Conference
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• 2007.10a
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• pp.189-190
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• 2007

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.68-76
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• 2015

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.506-514
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• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• Journal of IKEEE
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• v.16 no.1
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• pp.45-50
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• 2012

This paper proposes the methodology to estimate the routing congestion of modern IC quickly and accurately at the early stage of the design flow. The occurrence of over-congestion in the routing process causes routing failure which then takes unnecessary time to re-design the physical design from the beginning. The precise estimation of routing congestion at the early design stage leads to a successful physical design that minimizes over-congestion which in turn reduces the total design time cost. The proposed estimation method at the block-level floorplan stage measures accurate routing congestion by using the analyzed virtual interconnections of inter/intra blocks, synthesized virtual power/ground and clock networks.

• ETRI Journal
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• v.27 no.6
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• pp.691-696
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• 2005

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very-large-scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a $5{\times}5$ matrix of data cells in a Virtex-E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.