• ETRI Journal
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• v.28 no.4
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• pp.525-528
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• 2006

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A-MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system-on-a-chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is $7.5\;mm{\times}7.5\;mm$ (using 0.25 micron 4-layers metal CMOS technology).

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.2
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• pp.85-90
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• 2003

This paper has presented the efficient implementation of MPEG-4 simple profile video decoder, which is used as video compression standard in mobile video communication. We have used the ARM9 processor in implementing this MPEG-4 simple profile, which requires much processing power and low power implementation. At first we implemented with C-language under the PC environment with ADS(ARM Developer Suite) environment, and then we have tried to reduce a clock cycle for a power consumption optimization through conversion an assembly language for C-code partly. We have verified the processor is operated at 22.47MHz operation after optimization, but 148MHz before optimization.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.114-124
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• 2014

HEVC is a state-of-the-art video coding standard developed by JCT-VC. HEVC provides about 2 times higher subjective coding efficiency than H.264/AVC. One of the main goal of HEVC development is to efficiently coding UHD resolution video so that HEVC is expected to be widely used for coding UHD resolution video. Decoding such high resolution video generates a large number of memory accesses, so a decoding system needs high-bandwidth for memory system and/or internal communication architecture. In order to determine such requirements, this paper presents an analysis of the memory access complexity for HEVC decoder. we first estimate the amount of memory access performed by software HEVC decoder on an embedded system and a desktop computer. Then, we present the memory bandwidth models for HEVC decoder by analyzing the data flow of HEVC decoding tools. Experimental results show the software decoder produce 6.9-40.5 GB/s of DRAM accesses. also, the analysis reveals the hardware decoder requires 2.4 GB/s of DRAM bandwidth.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2120-2130
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• 1998

This paper concerns a design of programmable MPEG decoder for video processing by object unit on network. The decoder can process video data effectively by a embedded controller with stack buffers for supporting OOP (Object-Oriented Programming). The controller offers extended instructions that process several data types including 32bit integer type. In addition to that, we have a vector processor, in this decoder that can execute advanced compensation and prediction by half pixel and SA(Shape Adaptive)-IDCT of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We verified the decoder with $0.6\mu\textrm{m}$ 5-Volt CMOS COMPASS library.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.53-64
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• 2011

In this paper, we propose a channel estimation of side information method based received motion vectors for distributed video coding. The proposed decoder estimates motion vectors of side information and transmits it to the encoder. As the proposed encoder generates side information which is the same to one in the decoder with received motion vectors, accuracy of side information of the decoder is assessed and it is transmitted to decoder. The proposed decoder can also estimate accurate crossover probability with received error information. As the proposed method conducts correct belief propagation, computational complexity of the channel decoder decreases and error correction capability is significantly improved with the smaller amount of parity bits. Experimental results show that the proposed algorithm is better in rate-distortion performance and it is faster than several conventional distributed video coding methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.805-812
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• 2008

H.264 technology is considered as the heart of the next-generation video codec standard. Europe and other countries have actually specified H.264 technology as the video codec standard for HD broadcasting. However, due to the complexity of algorithm, it is still a difficult job to implement HD-level H.264 decoders in real-time software. In this paper, I have restricted a part of the decoding process, in order to implement an H.264 software video decoder which guarantees a real-time operation, and suggest an H.264 decoder that adaptively selects the algorithm to minimize image degradation. Performance of the suggested H.264 decoder was compared and verified through a PC simulation. As a consequence, when the suggested decoder was used in an environment where real-time decoding was difficult, it has achieved the minimal image degradation as well as real-time decoding in most cases.

• Journal of Broadcast Engineering
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• v.15 no.1
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• pp.112-121
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• 2010

Distributed video coding is a coding paradigm that allows complexity to be shared between encoder and decoder, in contrast with conventional video coding. We propose that complexity balancing method of encoder/decoder by phase motion estimation algorithm. The encoder performs partial motion estimation. The result of the partial motion estimation is transferred to the decoder, and the decoder performs motion estimation within the narrow range. When the encoder can afford some complexity, complexity balancing is possible. The method proposed is able to know relativity between complexity balancing and coding efficiency. The coding efficiency increase rate by the encoder complexity increases is higher than that by the decoder complexity increases. The proposed method can control the complexity and coding efficiency according to devices' resources and channel conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.621-627
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• 2010

This paper proposes an efficient architecture of Inter layer up-sampling in decoder for SVC(scalable video coding). A register bank for horizontal and vertical up-sampling and interpolation units are designed, by introducing the proposed architecture, 41% memory bandwidth is reduced compared to JSVM. For real-time operation for HD 6 layer decoder having CIF, SD, HD resolution for CGS layer, the hardware is designed to operate at 127MHz. The gate count is about 3000.

• Journal of Digital Contents Society
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• v.6 no.3
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• pp.169-174
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• 2005

In this paper we propose efficient design and implementation of JPEG image display board that can display JPEG image on TV. we used NAND Flash Memory to save the compressed JPEG bit stream and video encoder to display the decoded JPEG mage on TV. Also we convert YCbCr to RGB to super impose character on JPEG image. The designed B/D is implemented using FPGA.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.6
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• pp.418-429
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• 2016

In this paper, we propose a hybrid Wyner-Ziv video coding structure that combines conventional motion predictive video coding and Wyner-Ziv video coding to eliminate the feedback channel, which is a major practical problem in applications using the Wyner-Ziv video coding approach. The proposed method divides a hybrid frame into two regions. One is coded by a motion predictive video coder, and the other by the Wyner-Ziv coding method. The proposed encoder estimates side information with low computational complexity, using the coding information of the motion predictive coded region, and estimates the number of syndrome bits required to decode the region. The decoder generates side information using the same method as the encoder, which also reduces the computational complexity in the decoder. Experimental results show that the proposed method can eliminate the feedback channel without incurring a significant rate-distortion performance loss.