• Journal for History of Mathematics
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• v.21 no.2
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• pp.71-80
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• 2008

From the ancient Korea, our ancestor had designed the unique pattern which is Dan-chung, in architectures such as palace and Buddhist temple. In Dan-chung pattern, there are many various kinds, that is geometric pattern, arabesque pattern, plant pattern, flower pattern, animal pattern, Buddhist pattern and living pattern. So, we can see the tessellations in the Dan-chung pattern, moreover we can find the beauty of tessellation in the Korean traditional architectures and crafts. In this paper, I'll show you Korean traditional tessellations via GSP 4.0. which means geomeric program Geometer's SkechPad.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.55-67
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• 2010

The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.69-74
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• 2010

A new package substrate for dynamic random access memory(DRAM) devices has been developed using selective aluminum anodization. Unlike the conventional substrate structure commonly made by laminating epoxy-based core and copper clad, this substrate consists of bottom aluminum, middle anodic aluminum oxide and top copper. Anodization process on the aluminum substrate provides thick aluminum oxide used as a dielectric layer in the package substrate. Placing copper traces on the anodic aluminum oxide layer, the resulting two-layer metal structure is completed in the package substrate. Selective anodization process makes it possible to construct a fully filled via structure. Also, putting vias directly in the bonding pads and the ball pads in the substrate design, via in pad structure is applied in this work. These arrangement of via in pad and two-layer metal structure make routing easier and thus provide more design flexibility. In a substrate design, all signal lines are routed based on the transmission line scheme of finite-width coplanar waveguide or microstrip with a characteristic impedance of about $50{\Omega}$ for better signal transmission. The property and performance of anodic alumina based package substrate such as layer structure, design method, fabrication process and measurement characteristics are investigated in detail.

• Journal of Welding and Joining
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• v.29 no.1
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• pp.46-51
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• 2011

TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2217-2220
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• 2007

In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.

• Tribology and Lubricants
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• v.33 no.3
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• pp.112-118
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• 2017

Tilting pad journal bearings(TPJBs) are widely used for high speed rotating machinery owing to their rotordynamic stability and thermal management feature. With increase in the rotating speed of such machinery, an increasingly important aspect of TPJB design is the prediction of their thermal behaviors. Researchers have conducted detailed investigations in the last two decades, which provided design tools for the TPJBs. Based on these previous studies, this paper presents a thermohydrodynamic(THD) analysis model for TPJBs. To calculate pressure distribution, we solve the generalized Reynolds equation and to predict the lubricant temperature, we solve the 3D energy equation. We employ the oil mixing theory to calculate pad inlet temperature; further, to consider heat conduction via the pad, we solve the heat conduction equation for the pads. We assume the shaft temperature as the averaged oil film temperature and apply natural convection boundary conditions to the pad side and back surfaces. To validate the analysis model, we compare the predicted pad temperatures with those from previous research. The results show good agreement with previous research. In addition, we conduct parametric studies on a TPJB which was used in a gas turbine simulator system. The predicted results show that film temperature largely depends on the rotating speed and oil supply condition.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.1
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• pp.39-43
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• 2003

Thermal management is very important for the success of high density circuit design in LTCC. In this paper, LTCC substrates containing thermal via and pad were fabricated in order to study the influence of the thermal dissipation. To realize the accurate thermal analysis for structure design, a series of simple thermal conductivity measurement by laser flash method and parametric numerical analysis have been carried out. The LTCC substrate including via and Ag pad has good thermal conductivity over 103 W/mK which is 44% value of pure Ag material. Thermal behaviors with via arrays, size and density in the LTCC substrate were studied by numerical method.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2011.10a
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• pp.279-284
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• 2011

The calculation of Zwicker's loudness which is needed for multiple frequency response with a fine frequency resolution using the finite element (FE) procedure usually requires significant computation time since a numerical solution must be obtained for each considered frequency. Furthermore, if the analysis is the basis for an iterative optimization procedure this approach imposes high computational cost. In this work, we present an efficient approach for obtaining Zwicker's loudness via the Pad$\acute{e}$ approximants and applying in an acoustical topology optimization procedure. The paper is focused on an efficient and accurate calculation of Zwicker's loudness, design sensitivity analysis, and the acoustical topology optimization method by using Pad$\acute{e}$ approximants. The paper compares the efficient algorithm to results obtained by a standard FEM. Comparison are made both in terms of accuracy and in terms of CPU-times needed for the calculation.

• ETRI Journal
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• v.35 no.2
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• pp.340-343
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• 2013

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.76-81
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• 2011

A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.