• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.1
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• pp.40-47
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• 2014

Sinusoidal back-EMF waveform of vernier Permanent Magnet (PM) machines is analyzed in this paper. An analytical expression of Electromotive Force (EMF) of electric machines including vernier machines is developed to analyze EMF harmonics, and the effect of vernier PM machine pole ratio, the ratio of number of rotor poles to stator poles, on the EMF waveform. Moreover, this paper represents several Finite Element Analysis (FEA) models to verify the analysis based on the proposed expression, and the effect of tooth width ratio, which is the ratio of tooth width to tooth pitch, on back-EMF of vernier PM machines, and optimal tooth width ratio is obtained and verified by FEA. Finally, this paper makes comparisons between EMF waveform of vernier PM machines and that of traditional PM machines from the point of view of analytical EMF expression.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.1
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• pp.54-62
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• 2000

본 논문은 Vernier 모드에서 운전하는 2-모듈 TCSC로 구성된 전력송전시스템의 특성 해석을 위하여 싸이리스터 점호각 계산을 푸리에 공간에서 수행한다. 이를 위하여 싸이리스터 스위칭 함수를 이용하여 TCSC 리액터 전류에 관한 연립방정식을 구하였다. TCSC 모듈의 등가 임피던스가 전력송전 시스템이 요구하는 특정값을 갖게 하는 싸이리스터 점호각을 수치해석 방법을 사용하여 구하고, TCSC 전력송전시스템의 정상상태 특성을 해석하였다. 또한 EMTP 시뮬레이션을 수행하여 푸리에 공간에서의 점호각 계산의 타당성을 시평면상에서 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.546-555
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• 2013

In this paper, we propose a novel method to enhance the harmonic components from the frequency lines of the passive sonar signals. For this, we first separate the stable frequency lines from unstable ones using mean and difference of spectral bins in the vernier analysis. Then we emphasize the harmonic components using autocorrelation-based postprocessing, and enhance them by reducing the background noise with the split-window two pass mean algorithm. Experimental results for real underwater acoustic data are presented with our discussions.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.83-86
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• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.195-200
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• 2015

This paper presents SVBS-TDC (Semi-Vernier Binary-Search Time-to-Digital Converter) for the noise improvement of ADPLL (All-Digital Phase Locked Loop. We used a Semi-Vernier BS-TDC (Binary-Search TDC) architecture to improve the operation speed more then 10 times compared with the previous conventional BS-TDC and ensured a 510ps wide input range. The proposed Semi-Vernier BS-TDC was designed in a 65ns CMOS process and the simulation results showed 200MHz speed and 4ps resolution with a 1.2V supply voltage, and considerable noise improvement of ADPLL.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.411-417
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• 2012

A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in $0.18{\mu}m$ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ps with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ps.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1700-1706
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• 2016

In this paper, a dual-stator, spoke-type linear vernier machine (DSSLVM) for wave energy extraction application was proposed. This machine is capable of producing a competitively high thrust force and force density at a low operation speed in direct drive systems. The operation principal and working of the proposed DSSLVM were studied. The stator core height is adjusted to improve the overall force density of the proposed machine while reducing the force ripple. To evaluate the advantages of the proposed DSSLVM, the main performance was compared with that of a recently developed linear primary permanent magnet vernier machine (LPPMVM). The proposed machine exhibited greater thrust force and force density, an improved power factor and lower force ripple with the same permanent magnet (PM) volume compared to the LPPMVM.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.150-156
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• 2016

This paper compares the performances of permanent-magnet synchronous (PMS) and permanent-magnet vernier (PMV) machines for low-speed and high-torque applications. For comparison with the PMS machines, we consider two types of the PMV machine. The first one has surface-mounted permanent magnets (PMs) on the rotor and the other has PMs inserted on both sides of the stator and rotor. The PMS and PMV machines are designed to meet the condition of equal output power per unit volume. We analyze the magnetic fields of the machines using a two-dimensional finite element analysis (FEA). We then compare their performances in terms of the generated torque characteristics, power factor, loss, and efficiency.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1146-1151
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• 2013

This paper deals with design consideration and validation of a new pole-slot combination for permanent magnet vernier machine (PMVM) with consequent pole (CP) rotor especially for extremely low speed servo applications. A 136pole-24slot PMVM with CP rotor is introduced and analyzed by 2D and 3D finite element analysis (FEA) and discussion on experimental validation is also included.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.16-21
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• 2006

This paper shows a vernier delay technique for generating precise multiphase clocks using PLL structure. The proposed technique can achieve the finer timing resolution less than the gate delay of the delay chain in VCO. Using this technique, 62.5ps of timing resolution can be achieved if the reference clock rate is set at 1GHz using 0.18um CMOS technology. Jitter of 14ps peak-to-peak was measured.