• Title/Summary/Keyword: trinomial table

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A Study on the Hardware Architecture of Trinomial $GF(2^m)$ Multiplier (Trinomial $GF(2^m)$ 승산기의 하드웨어 구성에 관한 연구)

  • 변기영;윤광섭
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.41 no.5
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    • pp.29-36
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    • 2004
  • This study focuses on the arithmetical methodology and hardware implementation of low-system-complexity multiplier over GF(2$^{m}$ ) using the trinomial of degree a The proposed parallel-in parallel-out operator is composed of MR, PP, and MS modules, each can be established using the regular array structure of AND and XOR gates. The proposed multiplier is composed of $m^2$ 2-input AND gates and $m^2$-1 2-input XOR gates, and the propagation delay is $T_{A}$+(1+[lo $g_2$$^{m}$ ]) $T_{x}$ . Comparison result of the related multipliers of GF(2$^{m}$ ) are shown by table, it reveals that our operator involve more regular and generalized then the others, and therefore well-suited for VLSI implementation. Moreover, our multiplier is more suitable for any other GF(2$^{m}$ ) operational applications.s.