• Transactions of the Korean Society of Automotive Engineers
• /
• v.5 no.2
• /
• pp.69-79
• /
• 1997

This paper deals with the measurement and analysis on the scavenging performance of the oppet-valve type two-stroke engine with different shroud system. The scavenging flow characteristics is investigated by flow visualization under steady condition, in which a dye is introduced into single-cycle method using the difference of specific gravity between two working fluids is used to evaluate the scavenging efficiency and the trapping efficiency. The 90° shroud system was found to be the highest efficiency system through both flow visualization and single-cycle test, as well as the shroud system to generally be efficient for reducing a short-circuiting flow during scavenging process in a two-stoke engine.

• Electrical & Electronic Materials
• /
• v.10 no.1
• /
• pp.26-32
• /
• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.27 no.10
• /
• pp.648-652
• /
• 2014

We have investigated the effect of electrical properties of amorphous InGaZnO thin film transistors (a-IGZO TFTs) by post thermal annealing in $O_2$ ambient. The post-annealed in $O_2$ ambient a-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has better performance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well as reasonable threshold voltage, than others do. The interface trap density is controlled to achieve the optimum value of TFT transfer and output characteristics. The device performance is significantly affected by adjusting the annealing condition. This effect is closely related with the modulation annealing method by reducing the localized trapping carriers and defect centers at the interface or in the channel layer.

• Journal of Welding and Joining
• /
• v.24 no.3
• /
• pp.42-48
• /
• 2006

Since the voids occur at the CD stud welds, the mechanism of void formation and void reduction method are investigated in this work. It is speculated that the voids are formed because of high short-circuit current above 1000A. When the simple flow model is used to estimate the void trapping condition, the most voids are trapped at the weld mainly due to fast cooling rate of the CD stud weld. Since it is almost impossible to remove the voids completely, a method is proposed to reduce the void by decreasing the short-circuit current at the end of the arcing time. The experimental results show that the void is reduced by decreasing the short-circuit current to 1000A.

• Bulletin of the Korean Chemical Society
• /
• v.15 no.12
• /
• pp.1103-1107
• /
• 1994

Interaction of triethylsilane and diphenylsilane ($Ph_2$$SiH_2$, $Ph_2$$SiD_2$) with the surfaces of rhodium has been examined by trapping the reaction intermediates with 2,3-dimethyl-l,3-butadiene. 1,4-Hydrosilylation of the diene is predominantly observed to occur under mild condition over the rhodium catalyst. It is inferred from the product analyses that silylene and silyl radicals bonded to rhodium surfaces are the intermediates for addition of silylene to the diene, and for 1,4-hydrosilylation, respectively.

• Proceedings of the Earthquake Engineering Society of Korea Conference
• /
• 2000.10a
• /
• pp.81-88
• /
• 2000

The elastic wave equation is solved using the finite-difference method in 3D space to simulate the seismic wave propagation. It is based on the velocity-stress formulation of the equation of motion on a staggered grid. The nonreflecting boundary conditions are used to attenuate the wave field close to the numerical boundary. To satisfy the stress-free conditions at the free-surface boundary, a new formulation combining the zero-stress formalism with the vacuum one is applied. The effective media parameters are employed to satisfy the traction continuity condition across the media interface. With use of the moment-tensor components, the wide range of source mechanism parameters can be specified. The numerical experiments are carried out in order to test the applicability and accuracy of this scheme and to understand the fundamental features of the wave propagation under the generalized elastic media structure. Computational results show that the scheme is sufficiently accurate for modeling wave propagation in 3D elastic media and generates all the possible phases appropriately in under the given heterogeneous velocity structure. Also the characteristics of the ground motion in an sedimentary basin such as the amplification, trapping, and focusing of the elastic wave energy are well represented. These results demonstrate the use of this simulation method will be helpful for modeling the ground motion of seismological and engineering purpose like earthquake hazard assessment, seismic design, city planning, and etc..

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.10
• /
• pp.32-38
• /
• 2003

This works reports the measurement and analysis results on the hot electron induced device degradation in Gate-All-Around SOI MOSFET's, which were fabricated using commercially available SIMOX material. It is observed that the worst-case condition of the device degradation in nMOSFETs is $V_{GS}$ = $V_{TH}$ due to the higher impact ionization rate when the parasitic bipolar transistor action is activated. It is confirmed that the device degradation is caused by the interface state generation from the extracted degradation rate and the dynamic transconductance measurement. The drain current degradation with the stress gate voltages shows that the device degradation of pMOSFETs is dominantly governed by the trapping of hot electrons, which are generated in drain avalanche hot carrier phenomena.r phenomena.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.419-419
• /
• 2016

High efficiency silicon solar cell requires the textured front surface to reduce reflectance and to improve the light trapping. In case of mono-crystalline silicon solar cell, wet etching with alkaline solution is widespread. However, the alkali texturing methods are ineffective in case of multi-crystalline silicon wafer due to grain boundary of random crystallographic orientation. The acid texturing method is generally used in multi-crystalline silicon wafer to reduce the surface reflectance. However the acid textured solar cell gives low short-circuit current due to high reflectivity while it improves the open-circuit voltage. To reduce the reflectivity of multi-crystalline silicon wafer, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE experimental condition with change of RF power (100W, 150W, 200W, 250W, 300W). During experiment, the gas ratio of SF6 and O2 was fixed as 30:10.

• Journal of Korean Ophthalmic Optics Society
• /
• v.6 no.2
• /
• pp.121-127
• /
• 2001

While SVD and Gaussian elimination method were applied to the additive damped least squares(DLS), the convergence and the stability of the optimization process were examined in a triplet-type camera lens-system where the condition number is well conditioned. DLS with SVD method generated a suitable merit function but this merit function may be trapped in a local minimum by the nonlinearity of error function. Therefore, the least camera lens-system was further designed by the global optimization method is grid method, and this method is adopted to get merit function that convergent to global minimum without local minimum trapping.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.9-12
• /
• 1998

Film characteristics of thin reoxidized nitrided oxides were investigated by SIMS analysis and C-V method in order to use the gate dielectric for charge-trap type NVSMs instead of ONO stacked layers. Nitric oxide(NO) annealed film has the nitrogen content sharply peaked at the Si-SiO$_2$ interface, while it is broad for nitrous oxide($N_2$O) ambient. The nitrogen peak concentration increased with anneal temperature and time. The position of nitrogen content in the oxide layer was due to be precisely controlled. For the films annealed NO ambient at 80$0^{\circ}C$ for 30min. followed by reoxidized at 85$0^{\circ}C$, the maximum memory window of 3.5V was obtained and the program condition was +12V, 1msec for write and -l3V, 1msec for erase.