• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.6
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• pp.519-524
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• 2007

The OBC(on-board computer) of a satellite which plays a role of the controller for the satellite should be equipped with preventive measures against transient errors caused by SEU(single event upset). Since memory devices are pretty much susceptible to these transient errors, it is essential to protect memory devices against SFU. A common method exploits an error detection and correction code and additional memory devices, combined with periodic memory scrubbing. This paper proposes an effective memory scrubbing scheme for the OBC of STSAT-2. The memory system of the OBC is briefly mentioned and the reliability of the information stored in the memory system is analyzed. The result of the reliability analysis shows that there exist optimal scrubbing periods achieving the maximum reliability for allowed overall scrubbing overhead and they are dependent on the significance of the information stored. These optimal scrubbing periods from a reliability point of view are derived analytically.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.797-800
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• 2005

In this paper, the designed 10-bit current steering data driving circuit consists of bias circuits, shift registers, data and line latches, level shifters, and 10-bit D/A converters. This data driving circuit can improve image quality, driving speed, and can reduce process error, DNL error, and glitch noise. To reduce current cells, the 10-bit D/A converter was designed 3+3+4 hybrid type. As a result 49 current cells are decreased. The transient analysis shows that currents flows a few of mA in data line and the currents have 1024 gray levels of current values. Total circuits are designed for 10 ${\mu}s$ speed. Thus the designed 10-bit current steering data driving circuit can be usable in HDTV/XGA AMOLED displays. These data driving circuits are designed for 0.35 ${\mu}m$ CMOS process at 3.3 V and 18 V supply voltage and simulated with HSPICE..

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.805-814
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• 1994

In this paper, we introduce a new method which is available for analyzing the throughput of the packet radio network by using the auxiliary Markov transient matrix with a failure state and a success state. And we consider the effect of symbol error for the network state(X, R) consisted of the number of transmitting PRU X and receiving PRU R. We examine the packet radio network of a continuous time Markov chain model, and the direct sequence binary phase shift keying CDMA radio channel with hard decision Viterbi decoding and bit-by-bit changing spreading code. For the unslotted distributed multi-hop packet radio network, we assume that the packet error due to a symbol error of radio channel has Poisson process, and the time period of an error occurrence is exponentially distributed. Through the throughputs which are found as a function of radio channel parameters, such as the received signal to noise ratio and chips of spreading code per symbol, and of network parameters, such as the number of PRU and offered traffic rate, it is shown that this composite analysis enables us to combine the Markovian packet radio network model with a coded DS/BPSK CDMA radio channel.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.233-238
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• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• Transactions of the Korean Society of Mechanical Engineers
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• v.12 no.2
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• pp.221-230
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• 1988

In the microcomputer-based velocity control for an electro-hydraulic servo system, the effects of control methods and control hardware on the performance of the system were investigated. Experiments were carried out with PID and deadbeat controllers using 8 or 16 bit microprocessor and 8 or 12 bit A/D and D/A converters. It is found that the transient response of the system is better with PID controller than with deadbeat controller. When the number of bits of the microprocessor and converters are small, it is also found that amplitude quantization due to limited word-length gives significant effects on transient responses of the system. Analytically predicted step responses are in good agreement with experimental ones.

• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.274-281
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• 2011

High-speed telecommunication systems are influenced by electromagnetic environments because they need a wide bandwidth to transmit signals. Immunity tests of telecommunication equipment are effective for improving its immunity to electromagnetic environments. However, immunity tests are expensive to carry out because there are several different tests. The correlation among the tests should therefore be examined in order to reduce the kinds of tests that are necessary. This paper investigates the correlation between the electrical fast transient/burst (EFTB) test and the radio frequency (RF) conductive immunity test. Imitation equipment was constructed with a balun, and a baseband signal was transmitted from the associated equipment to the imitation equipment. Then, disturbances were applied to the equipment, and the telecommunication quality was evaluated by using the bit error rate (BER). The results from the EFTB test indicated that the BER was less than $6{\times}10^{-5}$ and the value was independent of the peak value. The results from the RF conductive immunity test indicated that the BER was affected by the longitudinal conversion loss (LCL).

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.575-580
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• 2004

The latest equipment automatic Intelligence of digital base done large size equipment appear in succession. That run by voltage electric current(mA, mV, ${\mu}A,\;{\mu}V$) that outline is microscopic of action of accuracy large size equipment of this digital base is bulk. Have received influence that is great in river electric field by installment that use computer. Most of domestic working voltage from service entrance extra-high voltage and working voltage of commercial frequency 60Hz working voltage 220V that use our country outside 1 country in interior of 22.900V for semiconductor use computer use digital installment of appliance as well as various smalls of digital base, middle, large size that safety is these fine voltage electric current that is not enough direct admonition hundred vast damage give can. Also, already act in surge circle and impulse transient phenomena such as several thousands, myriads, strong bit error more than billions time to digital fine electronic circuit by mistake use of using electric facility system of system electric power.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.701-713
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• 2009

This paper studies a method for reducing performance degradation due to losing sub-carrier orthogonality caused by power transient between physical channels in LTE uplink transmission. The pattern of inter-carrier interference(ICI) caused by power transient is different from what has been studied for doppler shift, in that its pattern occurs at front and rear sides of channels in each period of power transient. The reason of ICI's occurrence results from power difference between channels, power transient duration, multi-path channel delay spread, and numbers of sub-carrier. New criterion is proposed to find out number of taps of multi-tap equalizer enough to improve the ICI. The scheme is to determine the number of taps of multi-tap equalizer when a normalized interference or a normalized ICI is greater than a normalized noise. Simulation results show that the number of taps is flexibly adjusted according to SNR(Signal to Noise Ratio) of a received signal to improve Bit Error Rate(BER), while the complexity of the proposed scheme is reduced down to 88 percentage of the classical method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.103-109
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• 2006

OFDM system has a disadvantage of sensitiveness about the effect of the frequency offset caused by the discord of oscillators in transmitter and receiver. The frequency offset can be divided into integral part and decimal part. Although the frequency offset of integral part do not effect orthogonality between subcarriers, it makes the bit error probability become to 0.5 because of circular transient among transmitted data symbols. This paper proposes a new estimation scheme of the frequency offset of integral part by Maximum Likelihood (ML) demanding only one training symbol in multipath fading channel environment. This proposed scheme not only can reduce the number of training symbol but do not increase the complexity and it shows the better performance by simulation.