• Journal of IKEEE
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• v.12 no.2
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• pp.75-80
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• 2008

There are many researches to reduce power consumption of battery-operated Transceiver for 2.4 GHz smartRF applications. However, components such as processor, memory and LCD based power managements reach the limit of reducing power consumption. To overcome the limit, this research proposes novel low-power Transceiver and transceiver Hardware Design. Experimental results in the real smartRF Transceiver show that the proposed methods can reduce power consumption additionally than component based power managements.

• Journal of Digital Contents Society
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• v.17 no.3
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• pp.173-180
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• 2016

In this paper, a design of transceiver module for real-time wire and wireless robust integrated security system to solve the problem of conventional security system and its transceiver module is proposed. The presented robust integrated security system is designed with RF control unit and wireless transceiver module. A RF controller in transceiver module works as a low-power RF transceiver system. It is designed to use specific bandwidth stored in registers and manipulate RF power of transceiver by accessing the random values of registers. Operation algorithm for RF transceiver module is also presented. The designed transceiver module and the operation algorithm are implemented and verified by experiments.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.1
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• pp.29-34
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• 2009

In this paper, we design RF transceiver architecture and building blocks for impulse radio UWB system. Impulse radio UWB signal occupies the wide frequency band which is very low transmission power. So, it can minimize the interference effect with the other system. Using UWB technology, we obtain position awareness service. Therefore, we describe the RF transceiver architecture of direct conversion receiver and define the requirement of RF transceiver. Moreover, we implement a prototype RF transceiver based on the presented standard and verify a function and performance through the wireless data communication and ranging test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.8
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• pp.481-487
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• 2014

In this paper, we have proposed gigabit serial transceiver based on backplane architecture at the satellite communication digital transponder. The transponder supports the full combinational switching function with broadband multi-channel using programmable device - Xilinx space-grade Virtex-5 FPGA. In order to implement the switching function, GTX transceiver solution inside Virtex-5 FPGA is used. Also hardware implementation is simple because of no additional component. In order to use a GTX transceiver, signal integrity(SI) simulation of PCB design is essential. We investigate the characteristics of the S-parameter, eye diagram, channel jitter of GTX transmission line and conform that GTX Transceiver operates without error. Finally the proposed PCB design will be utilized at satellite communication digital transponder EQM-2(Engineering Qualification Model-2).

• Journal of Advanced Navigation Technology
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• v.6 no.4
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• pp.296-305
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• 2002

This paper suggests the parameters of the requirement conditions of minimum performance for a RF transceiver system design from the specifications of IEEE Std 802.11b and IEEE Std 802.11a. It has yielded the requirement conditions of minimum performance in the design process due to these parameters. A RF transceiver system is simulated by using Agilent ADS(Advanced Design System) after selecting the components of optimal conditions to fabricate the RF transceiver system. The results of both the analysis and the simulation will be used for a real wireless LAN design.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.482-491
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• 2013

This paper explains modeling and analysis of RC-dominant wires for high-speed wireline transceiver design. A closed form formula derived from telegrapher's equation accurately describes a frequency response of an RC-dominant wire, yet it is simple and intuitive for designers to easily understand design trade-offs without a complex numerical equation solver. This paper explains how the model is derived and how it can help designers in example transceiver designs.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.131-134
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• 2000

This paper presents the circuit design and implementation of a HomePNA (Home Phoneline Network Alliance) 1M8 PHY transceiver for specification ver1.1. This paper describes a physical medium interface, an Ethernet MAC controller unit interface, and a management interface of the HomePNA transceiver. The designed HomePNA transceiver can support any specifications having more than 32Mbits/sec(maximum in HomePNA ver2.0) transmission rate by changing physical medium interface, because Ethernet MAC controller unit interface has been designed by using MII.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.10
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• pp.1917-1922
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• 2010

Near-Field Communication (NFC) is a short-range wireless communication technology evolved from RFID especially for the exchange of data between active and passive devices. This paper presents the mathematical models for the signal path of a NFC transceiver system and a behavioral simulation platform using MATLAB simulink. The approximated mathematical models simplify the simulation complexity of a transceiver and provide a quick evaluation. With this calculation platform, we can evaluate the system performance caused by the noise and the non-linearity of the individual blocks, and caused by system variables such as Effective Number of Bits (ENOB) of ADC and filter cutoff frequency. This platform provides us with a rapid prototyping, a reliable system design, and an efficient risk management during development of the NFC transceiver ICs.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.2
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• pp.34-39
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• 2007

UWB(Ultra Wide Band) system for high speed and high accurate location has been studying actively. This paper presents the design and implementation of RF transceiver for DS-CDMA(Direct Sequence-Code Division Multiple Access) UWB device. Major components of RF transceiver such as Low Noise Amplifier(LNA) and Band Pass Filter(BPF) are designed and then fabricated to meet wideband characteristics. The RF transceiver was implemented by the use of the fabricated components and commercial devices after carrying out performance simulation. Through the performance evaluation of the UWB RF transceiver with W-CDMA signal, the approach of design, implementation and evaluation of RF transceiver which is available to DS-CDMA UWB system is verified.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1185-1188
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• 2003

This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25 ${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L.