• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.173-179
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• 2002

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.292-299
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• 2015

An envelope elimination and restoration transmitter that uses a tri-level envelope encoding scheme is presented for improving the efficiency and linearity of the system. The proposed structure amplifies the same magnitude signal regardless of the input peak-to-average power ratio and reduces the quantization noise by spreading out the noise to the out-of-band frequency, resulting in the enhancement of power efficiency. An improved linearity is also obtained by providing a new timing mismatch calibration technique between the envelope and phase signal. Implementation in a 130 nm CMOS process, transmitter measurements on a 20-MHz long-term evolution input signal show an error vector magnitude of 3.7 % and an adjacent channel leakage ratio of 37.5 dBc at 2.13 GHz carrier frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1139-1144
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• 2008

In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform $100x{\tims}1000x$ faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.6
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• pp.612-619
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• 2004

Servo motor systems with ball-screw and timing-belt are widely used in NC, robot, FA and industrial applications. However, the nonlinear friction torque and damping effect in machine elements reduce the control performance. Especially tracking errors in trajectory control and very low velocity control range are serious due to the break-away friction and Stribeck effects. In this paper, a new double speed controller is proposed for compensation of the nonlinear friction torque. The proposed double speed controller has outer speed controller and inner friction torque compensator. The proposed friction torque compensator compensates the nonlinear friction torque with actual speed and speed error information. Due to the actual information for friction torque compensator without parameters and mathematical model of motor, proposed compensator is very simple structure and the stability is very high. The proposed compensator is verified by simulation and experimental results.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.38-45
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• 2014

This paper proposes a characterization method based on the reference memory to characterize memory compiler quickly and accurately. In order to maintain the accuracy of the memory complier and to minimize characterization time, the proposed method models the trends of the generated memories by selecting the reference memories after analyzing the timing trends of the memory compiler. To validate the proposed method, we characterized the 110nm memory compiler derived from 130nm memroy compiler. The average error rate of the characteristics of the memories generated by the proposed method and SPICE simulation is lower than ${\pm}0.1%$. Furthermore, we designed memory BIST test chips at 110nm and 180nm processes and the results of the function test show that the yield is 98.8% and 98.3%, respectively. Therefore, the proposed method is useful to characterize the memory compiler.

• Research in Community and Public Health Nursing
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• v.4 no.2
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• pp.170-187
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• 1993

The natural growth rate of the Korean population has decreased from 3.0% in 1960 to 1.0% in 1990. This was done with family planning program which was introduced by the government in 1961. The family planning program focused on birth control rather than the characteristics of the individuals and motivations of contraception. People were simply forced to use the method. Whereas, Natural Contraceptive is a method of family planning based solely on the timing of intercourse with the naturally occurring' physiological manifestation of fertilization and in fertilization during the menstrual cycle. This is the combination of self fertility awareness with periodic abstinence. Natural family .planning(NFP) programs in Korea were first started in the Chun-Chen diocese of catholic church by Bishop Thomas Stewart in 1970 In 1975, the Bishops conference launched the Korea Happy Family Movement in the Catholic Hospital Association, to promote the natural family planning. An average of 70,000 people, including adolescents, college students, unmarried and married persons, arid the clergies were trained during a six-year period (1986-1991). 61.5%(24,542 people) of those who completed 3 cycles during 6 year period (1986-1991) became autonomous users and the range was from 48.1% to 78.2%. In 1986, 22.7% of NFP individuals who drooped out of the program because of the desire for conception (23.4%), the difficulty of the method used(25.8%), and the loss of interest(22.8%). During the six-year period the unplanned pregnancy rate at the NFP was 2.9%. The range of the pregnancy rate was at 1.2-9.8%. The rate was decreased as years passed. The major reason for the failure of contraceptive was error by the individuals(61.1%). The percentage of the success of conception was 18.1% of 2.979 for achieving pregnancy. The highest percentage was 58.2% (99 users) in Kwang-Joo diocese and next was 37.1% (10 users) in Chong Joo diocese.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.290-297
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• 2014

The synchronization of OFDM receiver is consisted of symbol timing offset(STO) estimation in time domain and carrier frequency offset(CFO) estimation in frequency domain. This paper proposes new algorithm for correcting the integer CFO after we have done correcting the STO and partial CFO. ICFO must be corrected, since the ICFO lead to degrade bit error rate(BER) of demodulation performance. The PN sequence has information which is subcarrier order since the modified PN sequence, length is same subcarrier, is used in this paper and is modulated each subcarrier by each chip. Thus the receiver track phase of PN sequence after FFTin order to find the subcarrier frequency offset. The proposed algorithm is faster and more simple than convenient methode as measuring carrier energy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.322-330
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• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.261-269
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• 2013

In this paper, the evoked potential(EP) was represented by additive delay model to comply with the variational noisy response of stimulus-event synchronization. The hybrid method of delay compensated-Wiener filtered-ensemble averaging(DWEA) was proposed to enhance the EP signal distortion occurred during averaging procedure due to synchronization timing mismatch. The performance of DWEA has been tested by surrogated simulation, which is composed of synthesized arbitrary delay and arbitrary level of added noise. The performance of DWEA is better than those of Wiener filtered-ensemble averaging and of conventional ensemble averaging. DWEA is endurable up to added noise gain of 7 for 10 % mean square error limit. Throughout the experimentation observation, it has been demonstrated that DWEA can be applied to enhance the evoked potential having the synchronization mismatch with added noise.