• Journal of information and communication convergence engineering
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• 제8권4호
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• 한국정보기술학회 영문논문지
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• 제8권2호
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• pp.41-46
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• 2018

As evidenced through rapidly growing digital devices and information, digital authentication is becoming ever more critical, especially considering the complex and prevalent digital accounts we are using every day. Also, digital authentication is apt to consistent digital security application. In this sense, digital security quality and usability can be enhanced by developing a mechanism for efficient digital authentication. In this paper, a mechanism of efficient digital authentication called T-TIME is introduced in order to alleviate issues dealing with secure and user friendly authentication across ever- growing digital devices and information. Touch Signal generation time difference is utilized for T-TIME as a mediation mechanism that enhances the security quality by confusing others unlike other graphical password mechanisms which are using spatial information. Hence, digital authentication by using T-TIME can be a good way of enhancing security quality and usability.

• 대한전자공학회논문지SD
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• 제38권5호
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• pp.323-328
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• 2001

본 논문에서는 카운터와 커패시터를 사용하여 시간 정보로부터 디지털 출력 값을 얻을 수 있는 새로운 시간-디지털 변환기를 제안하였다. 기존의 시간-디지털 변환회로의 경우 디지털 출력 값을 얻기 위해서는 입력 신호가 인가된 후 입력 시간보다 더 긴 공정시간이 필요하였다. 또한 입력 신호의 시간 간격에 무관하게 카운터의 클럭 주파수가 일정하여 변환된 디지털 값의 분해도는 항상 일정하였다. 그러나 본 논문에서 제안한 시간-디지털 변환 회로는 입력 신호가 인가됨과 동시에 지연시간 없이 디지털 출력 신호를 얻을 수 있으며, 또한 수동소자의 값을 변화시킴으로서 원하는 입력 시간 영역과 분해도를 쉽게 구현할 수 있다.

• 한국실내디자인학회논문집
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• 제16권5호
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• pp.126-133
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• 2007

This study is intended to set the concept of becoming meaning of digital space through digital technology and to study the influence of digital space on becoming of real space through derived keyword. The results of this study are summarized as follows. First, the digital concept is created in the process that the virtual space is changed into the real space with a priority given to form, space and time. Digital expression concept and image concept the structural becoming, and idea concept and creative concept creates the time becoming. Second, the concept of digital becoming exposes a physical visibility through the digital's virtual image, and non-space spatiality through the space simulation. It also continuously reveals a consecutive time and non-consecutive time through a statable progress, incremental progress, and dynamic progress. Third, as the influence of digital on becoming of real space, the digital visibly not only expresses the new and difficult becoming problem through conceptual virtuality, but also can review the real space's space concept with virtuality in the digital non-area. Digital's durability expresses the new space's existence by physically combining with the existing space through the virtual form creation.

• 디지털산업정보학회논문지
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• 제13권3호
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• pp.35-42
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• 2017

This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.

• Journal of information and communication convergence engineering
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• 제8권1호
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• pp.103-106
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• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 추계학술대회
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• pp.522-523
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• 2017

전류컨베이어 회로와 시간-디지털 변화기를 이용하여 아날로그-디지털 변환기를 설계하였다. 전류컨베이어 회로를 이용하여 아날로그 전압의 크기를 샘플링한 다음, 전류원을 이용하여 샘플링 전압을 방전하면서 아날로그 전압을 시간정보로 변환하였다. 시간정보는 카운터 타입의 시간-디지털 변환기를 이용하여 디지털 값으로 변환되는데 이때 변환 에러를 감소시키기 위해 시간정보 펄스와 동기화된 클록을 생성하여 사용하였다.

• 대한전자공학회논문지
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• 제22권2호
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• pp.31-35
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• 1985

This paper presents novel designs of a digital minimum-time controller and a digital adaptive controller using reference no del for single input-single out put linear time-invariant plants with known parameters. The proposed digital minimum-time controller which has a deadbeat response is designed to make the transfer function of this controller equal to that of reference model, and the proposed digital adaptive controller is designed by applying the adaptation method to the proposed digital minimum-time controller. The designs of these two controllers are very simple and easy, and all types of input signal with any reference models are controllable. These dffectivenesses have been demon-strated by computer simulations carried out for a third-order plant.

• Journal of Power Electronics
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• 제11권2호
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• pp.156-162
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• 2011

The control loop time delay caused by sampling, the zero-order-holder effect and calculations is inevitable in the digital control of dc-dc switching converters. The time delay will limit the bandwidth of the control loop and therefore degrade the transient performance of digital systems. In this paper, the quantization time delay effects with different time delay values based on a generic second-order system are analyzed. The conclusion that the bandwidth of digital control is reduced by about 20% with a one cycle delay and by 50% with two cycles of delay in comparison with no time delay is obtained. To compensate the time delay and to increase the control loop bandwidth, a duty ratio predictive control scheme based on linear extrapolation is proposed. The compensation effect and a comparison of the load variation transient response characteristics with analogy control, conventional digital control and duty ratio predictive control with different time delay values are performed on a point-of-load Buck converter by simulations and experiments. It is shown that, using the proposed technique, the control loop bandwidth can be increased by 50% for a one cycle delay and 48.2% for two cycles of delay when compared to conventional digital control. Simulations and experimental results prove the validity of the conclusion of the quantization effects of the time delay and the proposed control scheme.

• 한국지능시스템학회논문지
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• 제10권5호
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• pp.423-431
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• 2000

In this paper, the effect of computing time-delay in the real-time digital fuzzy control systems is investigated and the design methodology of a real-time digital fuzzy controller(DFC) to overcome the problems caused by it is presented. We propose the fuzzy feedback controller whose output is delayed with unit sampling period. The analysis and the design problem considering computing time-delay is very easy because the proposed controller is syncronized with the sampling time. The stabilization problem of the digital fuzzy control system is solved by the linear matrix inequality(LMI) theory. Convex optimization techniques are utilized to find the stable feedback gains and a common positive definite matrix P for the designed fuzzy control system Furthermore, we develop a real-time fuzzy control system for backing up a computer-simulated truck-trailer with the consideration of the computing time-delay. By using the proposed method, we design a DFC which guarantees the stability of the real time digital fuzzy control system in the presence of computing time-delay.