• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.85-92
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• 2010

In this paper, we consider the orthogonal frequency division multiplexing (OFDM) based transmission incoorperating with beam-switching and space-time coding. Specifically, we consider three configurations; (1) the beamforming technique, (2) the spatial diversity technique and (3) their combination and evaluate the performance in wireless personal area network (WPAN) environment. For the beam-forming technique, we consider the beam-switching which is performed at RF front-end with a pre-defined set of beams and for the space-time coding, we consider the Alamauti scheme with antenna selection. For the combined scheme, we divide the antennas used into two group to generate two independent beams and apply the two-antenna Alamauti scheme over the two beams. For these three configurations, performance is evaluated in terms of the SNR gain.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.7-15
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• 2002

The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.2
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• pp.154-162
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• 2007

In this paper, we propose a new AC-DC converter control method to comply with harmonics regulation(IEC 61000-3) effective for the inverter system of an air conditioner whose power consumption is less than 2,500W. There are many different ways of AC-DC converter control, but this paper focuses on the converter control method that is adopting an input reactor with low cost silicon steel core to strengthen cost competitiveness of the manufacturer. The proposed control method controls input current every half cycle of the line frequency to get unit power factor and at the same time to reduce switching loss of devices and acoustic noise from reactor. This kind of converter is known as a Partial Switching Converter(PSC). In this study, theoretical analysis of the PSC has been performed using Matlab/Simulink while a 16-bit micro-processor based converter has been used to perform the experimental analysis. In the theoretical analysis, electrical circuit models and equations of the PSC are derived and simulated. In the experiments, micro-processor controls input current to keep the power factor above 0.95 by reducing the phase difference between input voltage and current and at the same time to maintain a reference DC-link voltage against voltage drop which depends on DC-link load. Therefore it becomes possible to comply with harmonic regulations while the power factor is maximized by optimizing the time of current flow through the input reactor for every half cycle of line frequency.

• The Korean Journal of Financial Management
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• v.21 no.2
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• pp.183-209
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• 2004

This paper uses both the bivariate GARCH type BEKK error correction model and Bivariate-AR(1)-Markov-Switching-VECM model to estimate the volatility, time-varying correlation and hedge ratio for the KTB spot and futures indexes, sampled daily over 1/4/2000-10/30/2003. This study suggests that the volatility regime has more significant influence on KTB markets than incline/decline regime does. The results support the importance of the bivariate model in stead of univariate model between KTB spot and futures markets, which may consider not only individual variance process but also covariance process at the same time.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.6
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• pp.64-73
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• 1997

RPWM(Random Pulse Width Modulation) techniques have been attracting an interest as an excellent reduction method of acoustic noise on the inverter drive system. Using randomly changed switching fre-quency of the inverter, the power spectrum of the electromagnetic acoustic noise can be spread out into the wide-band area. The wide band noise is much more comfortable and less annoying than the narrow-band one. This paper describes an implementationof the triangular carrier frequency modultde RPWM inverter drive system The poweer soedtrum of the noise emittde from the induction motro was measured in the anechoic chamber. The analysis of the sources for the acoustic noise and the effects of the noise reduction are confirmed by the ceasured dpectra of the noise. Real-time RPWM along with the speed control was achieved by high speed DSP(Digital Signal Processor ) TmS320C31, By changing the center frequency and the bandwidth of the carrier, theis real-time RPWM scheme can be used as an efficient switching frequency band acoustic noise reduction method for the inverter system with variant load conditions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.477-480
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• 2005

CMA-DD is proposed to improve the steady-state performance of CMA and its performance is depending on switching time between two modes of operation. Castro et al. who proposed a concurrent equalizer for solving problem of CMA-DD, which reduced the sensibility of switching time. However, concurrent algorithm has a problem that it keeps working after convergence. In this paper, we propose concurrent MCMA-DD equalizer combined modified CMA(MCMA) and DD mode for making better concurrent algorithm. The proposed equalizer is better than previous algorithm in convergence speed and steady-state performance. Also, the proposed algorithm decides optimum switching time using residual ISI of the equalizer output.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.3
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• pp.20-28
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• 2002

This paper describes the time sharing type high frequency resonant inviter can be used as power of induction heating. This closed inverter can be obtained output frequency three times than switching frequency by composing three unit inviter of conventional Half-Bridge serial resonant inverter in parallel with input power source also, this reduce switching loss because it has ZVS function. The analysis of the proposed circuit is generally described by using the normailized proposed parameters. The principle of basic operating and the its charasteristics are extimated by the parameters such as switching frequency($\mu$), the variation of Phase angle($\phi$) of Phase-shift. Experimental results are presented to verify theoretical discussion. This preposed inverter will be able to be prastically used as a power supply in various fields as induction, heating application, DC-DC converter etc.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.3
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• pp.57-66
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• 2011

The current trend of the handover authentication delay time is gradually increased according to the interworking between 3G cellular network and WLANs. Therefore, authentication mechanism minimized in delay is required to perform the seamless handover and support the inter-subnet and inter-domain handover. In this paper, we propose a novel pre-authentication scheme based on the fast channel switching which directly performs the authentication with the next access point in advance. In addition, the proposed scheme is efficient in the inter-domain handover and can be easily implemented in current WLANs since it just modifies the client side of user. To analysis and evaluate our scheme, we compare the packet loss ratio and the delay time with the two standard 802.11 authentication schemes. The analytical results show that our scheme is approximate 10 times more effective than the standard schemes in packet loss and the delay time is minimized down to 0.16 msec.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.103-108
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• 2006

This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.244-253
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• 2000

Since no single routing-switching combination performs the best under various different types of applications, a flexible network is required to support a range of polices. This paper introduces an implementation of a look-up table routing engine offering flexible routing and switching polices without performance degradation unlike those based on microprocessors. By deciding contents of look-up tables, the engine can implement wormhole routing, virtual cut-through routing, and packet switching, as well as hybrid switching, under a variety of routing algorithms. Since the routing engine has a piplelined look-up table architecture, the routing delay is as small as one flit, and thus it can overlap multiple routing actions without performance degradation in comparison with hardwired routers dedicated to a specific policy. Because four pipeline stages do not induce a hazard, expensive forwarding logic is not required. The routing engine can accommodate four physical links with a time shared cut-through bus or single link with a cross-bar switch. It is implemented using Xilinx 4000 series FPGA.