• 제목/요약/키워드: through-silicon via

검색결과 153건 처리시간 0.031초

위상잠금 적외선 현미경 관찰법을 이용한 다층구조 칩의 내부결함 위치 분석 (Internal Defect Position Analysis of a Multi-Layer Chip Using Lock-in Infrared Microscopy)

  • 김선진;이계승;허환;이학선;배현철;최광성;김기석;김건희
    • 비파괴검사학회지
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    • 제35권3호
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    • pp.200-205
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    • 2015
  • 현대의 컴팩트 반도체 소자들은 정확한 품질검사를 위해 비파괴, 고분해능의 검사 장비가 요구되고 있다. 검사 장비 중 고분해능 적외선 대물렌즈와 적외선 센서로 구성된 초정밀 열영상 현미경은 반도체 내부의 결함에서 발생되는 국소적 열원의 위치와 깊이 정보를 얻는데 유용하게 활용되고 있다. 본 연구에서는 위 상잠금기법이 적용된 적외선열영상 현미경을 이용하여 다층구조로 된 반도체 소자 내부 열원의 위치와 깊이 정보에 대해 분석하였다. 시편은 내부에 3개의 열원을 포함한 TSV(through silicon via technology) 기반 4단 적층구조로서 측정 표면으로부터 열원의 깊이는 $240{\mu}m$이다. 본 실험에서는 위상잠금기법을 통해 시편 내부열원의 위치와 깊이를 정확히 찾을 수 있는 초점면 위치, 노출시간 그리고 위상잠금주파수 등 최적의 조건을 찾고 그 조건에서 적외선 대물렌즈와 시편의 거리 변화에 따른 위상 변이와 깊이 정보에 대한 영향을 알아보았다. 이와 같은 반도체 내부결함에 의한 열원의 위치와 깊이 분석에 대한 연구는 품질검사용 열영상 분석장비 개발에 큰 도움을 줄 것으로 예상한다.

Optimization of Etching Profile in Deep-Reactive-Ion Etching for MEMS Processes of Sensors

  • Yang, Chung Mo;Kim, Hee Yeoun;Park, Jae Hong
    • 센서학회지
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    • 제24권1호
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    • pp.10-14
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    • 2015
  • This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

3D NoC 구조에서 성능을 고려한 어댑티브 수직 스로틀링 기반 동적 열관리 기법 (Performance-aware Dynamic Thermal Management by Adaptive Vertical Throttling in 3D Network-on-Chip)

  • 황준선;한태희
    • 전자공학회논문지
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    • 제51권7호
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    • pp.103-110
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    • 2014
  • 최근 등장한 TSV(Through Silicon Via)기반의 3D 적층 기술은 보다 강력한 발열관리 기법을 필요로 하며 냉각 비용과 폼팩터(form factor)의 제한을 고려했을 때 소프트웨어적인 열관리 기법의 중요성이 더욱 강조되고 있다. 이러한 접근 방식의 유력한 후보 중 하나로 제시되었던 스로틀링을 통한 열관리 기법의 경우, 증가하는 버스 점유율로 인해 전체적인 성능저하를 야기하는 문제점이 있다. 본 논문에서는 향후 TSV 기반 3D SoC의 커뮤니케이션 병목 현상을 해결하기 위한 3D 네트워크-온-칩 (Network-on-Chip, NoC) 구조에서 어댑티브 스로틀링 기법을 제안하여, 열관리와 더불어 온-칩 네트워크상의 트래픽 감소를 통해 전체적인 성능향상을 목표로 한다. 본 논문에서는 실험을 통하여 기존의 방식에 비하여 스로틀링으로 인해 저하된 처리량이 최소경로 라우팅 시 최대 72% 향상됨을 알 수 있었다.

SLS 공정을 이용한 p-type poly-Si TFT 제작에 관한 연구 (A Study on the Fabrication of p-type poly-Si Thin Film Transistor (TFT) Using Sequential Lateral Solidification(SLS))

  • 이윤재;박정호;김동환
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제51권6호
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    • pp.229-235
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    • 2002
  • This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.

나노리소그라피 기술을 이용한 초소수성 불소 실란 분자의 나노패턴 제조 (Fabrication of Superhydrophobic molecules Nanoarray by Dip-pen Nanolithography)

  • 연경흠;강필선;김경민;임정혁
    • 접착 및 계면
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    • 제19권4호
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    • pp.163-166
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    • 2018
  • 이 딥펜 나노리소그라피(DPN)는 원자 힘 현미경(AFM)을 기반으로 하는 나노 및 마이크로 패턴 제조 기술이다. 다양한 잉크 물질을 AFM 탐침에 코팅하여 탐침과 기판 사이에 형성된 물 메니스커스를 통해 기판으로 전이시켜 패턴을 제조한다. 본 연구에서는, 실란 전처리된 AFM 탐침 표면에 불소 실란 잉크 용액을 코팅하고 하이드록시기로 개질된 실리콘 기판 위에 접촉시킨 후, DPN 기술을 이용하여 표면으로 잉크 물질을 전이시키는 연구를 진행하였다. HDFDTMS 잉크 물질의 dot 어레이 패턴을 안정적으로 제조하였으며, AFM 탐침과 기판 사이의 접촉시간에 따라 패턴 크기가 선형적으로 증가하는 전형적인 DPN의 확산 메커니즘을 보였다.

반도체 및 전자패키지의 방열기술 동향 (Heat Dissipation Trends in Semiconductors and Electronic Packaging)

  • 문석환;최광성;엄용성;윤호경;주지호;최광문;신정호
    • 전자통신동향분석
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    • 제38권6호
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    • pp.41-51
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    • 2023
  • Heat dissipation technology for semiconductors and electronic packaging has a substantial impact on performance and lifespan, but efficient heat dissipation is currently facing limited improvement. Owing to the high integration density in electronic packaging, heat dissipation components must become thinner and increase their performance. Therefore, heat dissipation materials are being devised considering conductive heat transfer, carbon-based directional thermal conductivity improvements, functional heat dissipation composite materials with added fillers, and liquid-metal thermal interface materials. Additionally, in heat dissipation structure design, 3D printing-based complex heat dissipation fins, packages that expand the heat dissipation area, chip embedded structures that minimize contact thermal resistance, differential scanning calorimetry structures, and through-silicon-via technologies and their replacement technologies are being actively developed. Regarding dry cooling using single-phase and phase-change heat transfer, technologies for improving the vapor chamber performance and structural diversification are being investigated along with the miniaturization of heat pipes and high-performance capillary wicks. Meanwhile, in wet cooling with high heat flux, technologies for designing and manufacturing miniaturized flow paths, heat dissipating materials within flow paths, increasing heat dissipation area, and reducing pressure drops are being developed. We also analyze the development of direct cooling and immersion cooling technologies, which are gradually expanding to achieve near-junction cooling.

The Development of an Electroconductive SiC-ZrB2 Ceramic Heater through Spark Plasma Sintering

  • Ju, Jin-Young;Kim, Cheol-Ho;Kim, Jae-Jin;Lee, Jung-Hoon;Lee, Hee-Seung;Shin, Yong-Deok
    • Journal of Electrical Engineering and Technology
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    • 제4권4호
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    • pp.538-545
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    • 2009
  • The SiC-$ZrB_2$ composites were fabricated by combining 30, 35, 40 and 45vol.% of Zirconium Diboride (hereafter, $ZrB_2$) powders with Silicon Carbide (hereafter, SiC) matrix. The SiC-$ZrB_2$ composites, the sintered compacts, were produced through Spark Plasma Sintering (hereafter, SPS), and its physical, electrical, and mechanical properties were examined. Also, the thermal image analysis of the SiC-$ZrB_2$ composites was examined. Reactions between $\beta$-SiC and $ZrB_2$ were not observed via X-Ray Diffractometer (hereafter, XRD) analysis. The relative density of the SiC+30vol.%$ZrB_2$, SiC+35vol.%$ZrB_2$, SiC+40vol.%$ZrB_2$, and SiC+45vol.%$ZrB_2$ composites were 88.64%, 76.80%, 79.09% and 88.12%, respectively. The XRD phase analysis of the sintered compacts demonstrated high phase of SiC and $ZrB_2$ but low phase of $ZrO_2$. Among the SiC-$ZrB_2$ composites, the SiC+35vol.%$ZrB_2$ composite had the lowest flexural strength, 148.49MPa, and the SiC+40vol.%$ZrB_2$ composite had the highest flexural strength, 204.85MPa, at room temperature. The electrical resistivities of the SiC+30vol.%$ZrB_2$, SiC+35vol.%$ZrB_2$, SiC+40vol.%$ZrB_2$ and SiC+45vol.%$ZrB_2$ composites were $6.74\times10^{-4}$, $4.56\times10^{-3}$, $1.92\times10^{-3}$, and $4.95\times10^{-3}\Omega{\cdot}cm$ at room temperature, respectively. The electrical resistivities of the SiC+30vol.%$ZrB_2$, SiC+35vol.%$ZrB_2$ SiC+40vol.%$ZrB_2$ and SiC+45[vol.%]$ZrB_2$ composites had Positive Temperature Coefficient Resistance (hereafter, PTCR) in the temperature range from $25^{\circ}C$ to $500^{\circ}C$. The V-I characteristics of the SiC+40vol.%$ZrB_2$ composite had a linear shape. Therefore, it is considered that the SiC+40vol.%$ZrB_2$ composite containing the most outstanding mechanical properties, high resistance temperature coefficient and PTCR characteristics among the sintered compacts can be used as an energy friendly ceramic heater or electrode material through SPS.

저유전체 고분자 접착 물질을 이용한 웨이퍼 본딩을 포함하는 웨이퍼 레벨 3차원 집적회로 구현에 관한 연구 (A Study on Wafer-Level 3D Integration Including Wafer Bonding using Low-k Polymeric Adhesive)

  • 권용재;석종원
    • Korean Chemical Engineering Research
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    • 제45권5호
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    • pp.466-472
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    • 2007
  • 웨이퍼 레벨(WL) 3차원(3D) 집적을 구현하기 위해 저유전체 고분자를 본딩 접착제로 이용한 웨이퍼 본딩과, 적층된 웨이퍼간 전기배선 형성을 위해 구리 다마신(damascene) 공정을 사용하는 방법을 소개한다. 이러한 방법을 이용하여 웨이퍼 레벨 3차원 칩의 특성 평가를 위해 적층된 웨이퍼간 3차원 비아(via) 고리 구조를 제작하고, 그 구조의 기계적, 전기적 특성을 연속적으로 연결된 서로 다른 크기의 비아를 통해 평가하였다. 또한, 웨이퍼간 적층을 위해 필수적인 저유전체 고분자 수지를 이용한 웨이퍼 본딩 공정의 다음과 같은 특성 평가를 수행하였다. (1) 광학 검사에 의한 본딩된 영역의 정도 평가, (2) 면도날(razor blade) 시험에 의한 본딩된 웨이퍼들의 정성적인 본딩 결합력 평가, (3) 4-점 굽힘시험(four point bending test)에 의한 본딩된 웨이퍼들의 정량적인 본딩 결합력 평가. 본 연구를 위해 4가지의 서로 다른 저유전체 고분자인 benzocyclobutene(BCB), Flare, methylsilsesquioxane(MSSQ) 그리고 parylene-N을 선정하여 웨이퍼 본딩용 수지에 대한 적합성을 검토하였고, 상기 평가 과정을 거쳐 BCB와 Flare를 1차적인 본딩용 수지로 선정하였다. 한편 BCB와 Flare를 비교해 본 결과, Flare를 이용하여 본딩된 웨이퍼들이 BCB를 이용하여 본딩된 웨이퍼보다 더 높은 본딩 결합력을 보여주지만, BCB를 이용해 본딩된 웨이퍼들은 여전히 칩 back-end-of-the-line (BEOL) 공정조건에 부합되는 본딩 결합력을 가지는 동시에 동공이 거의 없는 100%에 가까운 본딩 영역을 재현성있게 보여주기 때문에 본 연구에서는 BCB가 본딩용 수지로 더 적합하다고 판단하였다.

무전해 도금법으로 제조된 Co(Re,P) capping layer제조 및 특성 평가 (Synthesis and Characterization of The Electrolessly Deposited Co(Re,P) Film for Cu Capping Layer)

  • 한원규;김소진;주정운;조진기;김재홍;염승진;곽노정;김진웅;강성군
    • 한국재료학회지
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    • 제19권2호
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    • pp.61-67
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    • 2009
  • Electrolessly deposited Co (Re,P) was investigated as a possible capping layer for Cu wires. 50 nm Co (Re,P) films were deposited on Cu/Ti-coated silicon wafers which acted as a catalytic seed and an adhesion layer, respectively. To obtain the optimized bath composition, electroless deposition was studied through an electrochemical approach via a linear sweep voltammetry analysis. The results of using this method showed that the best deposition conditions were a $CoSO_4$ concentration of 0.082 mol/l, a solution pH of 9, a $KReO_4$ concentration of 0.0003 mol/l and sodium hypophosphite concentration of 0.1 mol/L at $80^{\circ}C$. The thermal stability of the Co (Re,P) layer as a barrier preventing Cu was evaluated using Auger electron spectroscopy and a Scanning calorimeter. The measurement results showed that Re impurities stabilized the h.c.p. phase up to $550^{\circ}C$ and that the Co (Re,P) film efficiently blocked Cu diffusion under an annealing temperature of $400^{\circ}C$ for 1hr. The good barrier properties that were observed can be explained by the nano-sized grains along with the blocking effect of the impurities at the fast diffusion path of the grain boundaries. The transformation temperature from the amorphous to crystal structure is increased by doping the Re.

Enterococcus faecium LKE12 Cell-Free Extract Accelerates Host Plant Growth via Gibberellin and Indole-3-Acetic Acid Secretion

  • Lee, Ko-Eun;Radhakrishnan, Ramalingam;Kang, Sang-Mo;You, Young-Hyun;Joo, Gil-Jae;Lee, In-Jung;Ko, Jae-Hwan;Kim, Jin-Ho
    • Journal of Microbiology and Biotechnology
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    • 제25권9호
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    • pp.1467-1475
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    • 2015
  • The use of microbial extracts containing plant hormones is a promising technique to improve crop growth. Little is known about the effect of bacterial cell-free extracts on plant growth promotion. This study, based on phytohormonal analyses, aimed at exploring the potential mechanisms by which Enterococcus faecium LKE12 enhances plant growth in oriental melon. A bacterial strain, LKE12, was isolated from soil, and further identified as E. faecium by 16S rDNA sequencing and phylogenetic analysis. The plant growth-promoting ability of an LKE12 bacterial culture was tested in a gibberellin (GA)-deficient rice dwarf mutant (waito-C) and a normal GA biosynthesis rice cultivar (Hwayongbyeo). E. faecium LKE12 significantly improved the length and biomass of rice shoots in both normal and dwarf cultivars through the secretion of an array of gibberellins (GA1, GA3, GA7, GA8, GA9, GA12, GA19, GA20, GA24, and GA53), as well as indole-3-acetic acid (IAA). To the best of our knowledge, this is the first study indicating that E. faecium can produce GAs. Increases in shoot and root lengths, plant fresh weight, and chlorophyll content promoted by E. faecium LKE12 and its cell-free extract inoculated in oriental melon plants revealed a favorable interaction of E. faecium LKE12 with plants. Higher plant growth rates and nutrient contents of magnesium, calcium, sodium, iron, manganese, silicon, zinc, and nitrogen were found in cell-free extract-treated plants than in control plants. The results of the current study suggest that E. faecium LKE12 promotes plant growth by producing GAs and IAA; interestingly, the exogenous application of its cell-free culture extract can be a potential strategy to accelerate plant growth.