• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.911-913
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• 2008

In this work, nonvolatile memory (NVM) devices for system on panel of flat panel display (FPD) were fabricated using low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) technology with an oxide-nitride-oxynitride (ONOn) stack structure on glass. The results demonstrate that the NVM devices fabricated using the ONOn stack structure on glass have suitable switching characteristics for data storage with a low operating voltage, a threshold voltage window of more than 1.8 V between the programming and erasing (P/E) states after 10 years and its initial threshold voltage window (${\Delta}V_{TH}$) after $10^5$ P/E cycles.

• Nanomaterials
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• 제12권11호
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• pp.1808-1817
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• 2022

A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (V_th) window, which is crucial for NAND operation. The energetic-trap distribution is a critical material property of the CTN that affects the V_th window between the erase and program V_th. An artificial neural network (ANN) was used to model the relationship between the energetic-trap distributions as an input parameter and the V_th window as an output parameter. A well-trained ANN was used with the gradient-descent method to determine the specific inputs that maximize the outputs. The trap densities (N_TD and N_TA) and their standard deviations (σ_TD and σ_TA) were found to most strongly impact the V_th window. As they increased, the V_th window increased because of the availability of a larger number of trap sites. Finally, when the ML-optimized energetic-trap distributions were simulated, the V_th window increased by 49% compared with the experimental value under the same bias condition. Therefore, the developed ML technique can be applied to optimize cell transistor processes by determining the material properties of the CTN in 3D NAND Flash.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.864-867
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• 2003

Since the development of semiconductors, various related research has been conducted. During research, silicon diodes have been commonly used because of their simplicity and low cost in the manufacturing process. This research deals with p-n junction threshold voltages from silicon diodes due to transport current at a cryogenic temperature. At a cryogenic temperature(77K) we could get minimum current which junction threshold voltage becomes constant. This is experimented on GPIB communication and it consist of programmable current source, multimeter which gauge the threshold voltage in a very low temperature caused by transport current from 5nA to 1mA and $LN_2$(77K) for coolant. This experiment is programmed all process using Measurement studio(Lab window) tool.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• 전기전자학회논문지
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• 제23권4호
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• pp.1224-1229
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• 2019

본 연구에서는 블라인드와 같은 스마트 윈도우 응용을 위해 액정 셀을 제작하였고, 광 투과율이 조절되는 시스템을 개발하였다. 액정 셀의 문턱전압은 1.325V였고, 투과율이 10%일 때 전압은 2.370V를 보여 제작된 액정 셀은 저전압으로 구동됨을 나타내었다. 또한, 액정 셀은 30ms 미만의 응답속도와 80℃/10분간 열을 가한 후에도 안정하게 구동되었다. 구동 시스템은 액정 셀의 인가되는 전압을 0.15V에서 3.53V까지 약 0.5V 간격으로 설계하였고, 실제 인가되는 전압에 따라 액정의 광 투과율이 변화됨을 확인하였다. 이러한 결과는 액정 셀이 스마트 윈도우 응용이 가능성이 있음을 시사한다.

• 한국전기전자재료학회논문지
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• 제19권11호
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• pp.994-999
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• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

• 공업화학
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• 제30권2호
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• pp.205-211
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• 2019

지난 수십 년 동안 고분자 분산형 액정(polymer dispersed liquid crystal, PDLC)은 전기광학적으로 전환이 가능한 특성으로 인해 빛의 투과도를 자유롭게 조절할 수 있는 smart window를 개발하는 물질로서 주목을 받아왔다. 본 연구에서는 높은 구동전압과 낮은 명암비 등의 PDLC 문제점을 해결하기 위해 아크릴계 단량체 2-hydroxyethyl acrylate (2-HEA)와 ethylene glycol phenyl ether acrylate (EGPA)의 조성이 PDLC의 전기광학 특성에 미치는 영향을 평가하였다. 상온에서 10 cps 이하의 낮은 점도를 나타내는 2-HEA와 EGPA 단량체를 사용하여 제조하는 경우 보다 쉽게 capillary action에 의해서 indium tin oxide (ITO) glass 사이에 주입하는 공정이 가능하였다. Phenyl group를 포함한 EGPA 단량체가 대부분으로 이루어진 1 : 9인 단량체 혼합물로 만들어진 PDLC cell의 경우 전기장을 인가하지 않은 경우에도 불투명한 상태가 관측되지 않았고 인가 전압에 따라 매우 불안정한 투과율을 나타내었다. Cell gap thickness가 증가함에 따라 문턱전압(threshold voltage, $V_{th}$)과 포화전압(saturation voltage, $V_{sat}$)도 증가하는 경향을 나타내었으며, $20{\mu}m$의 cell gap thickness를 갖는 PDLC cell이 10과 $40{\mu}m$의 경우 보다 상대적으로 높은 명암비를 나타내었다. 특히, 7 : 3 비율의 2-HEA : EGPA 단량체 혼합물을 사용하여 제조된 PDLC cell의 경우가 낮은 구동전압과 높은 명암비의 가장 우수한 전기광학적 특성을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.324-326
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• 2016

In this study, we have investigated indium tin zinc oxide (ITZO) as an active channel for non-volatile memory (NVM) devices. The electrical and memory characteristics of NVM devices using multi-stack gate insulator SiO2/SiOx/SiOxNy (OOxOy) with Si-rich SiOx for charge storage layer were also reported. The transmittance of ITZO films reached over 85%. Besides, ITZO-based NVM devices showed good electrical properties such as high field effect mobility of 25.8 cm2/V.s, low threshold voltage of 0.75 V, low subthreshold slope of 0.23 V/dec and high on-off current ratio of $1.25{\times}107$. The transmission Fourier Transform Infrared spectroscopy of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000-2300 cm-1. It indicates that many silicon phases and defect sources exist in the matrix of the SiOx films. In addition, the characteristics of NVM device showed a retention exceeding 97% of threshold voltage shift after 104 s and greater than 94% after 10 years with low operating voltage of +11 V at only 1 ms programming duration time. Therefore, the NVM fabricated by high transparent ITZO active layer and OOxOy memory stack has been applied for the flexible memory system.

• 전기학회논문지P
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• 제57권2호
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• pp.135-139
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• 2008

MFISFETs with platinum electrode on the $LiNbO_3$/aluminum nitride/Si(100) structures were successfully fabricated and the properties of the FETs have been discussed. $I_D-V_G$ characteristics of MFISFETs for linear region (that is, 0.1 V of the drain voltage) showed hysteresis loop with a counter-clockwise trace due to the ferroelectric nature of $LiNbO_3$ films. A memory window (i.e., threshold voltage shift) of the fabricated device was about 2[V] for a sweep from -4 to +4[V]. The estimated field-effect electron mobility and transconductance on a linear region were 530[$cm^2/V{\cdot}s$] and 0.16[mS/mm], respectively. The drain current of 27[${\mu}A$] on the "on" state was more than 3 orders of magnitude larger than that of 30[nA] on the "off" state at the same "read" gate voltage of l.5[V], which means the memory operation of the MFISFET.