• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.911-913
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• 2008

In this work, nonvolatile memory (NVM) devices for system on panel of flat panel display (FPD) were fabricated using low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) technology with an oxide-nitride-oxynitride (ONOn) stack structure on glass. The results demonstrate that the NVM devices fabricated using the ONOn stack structure on glass have suitable switching characteristics for data storage with a low operating voltage, a threshold voltage window of more than 1.8 V between the programming and erasing (P/E) states after 10 years and its initial threshold voltage window (${\Delta}V_{TH}$) after $10^5$ P/E cycles.

• Nanomaterials
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• v.12 no.11
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• pp.1808-1817
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• 2022

A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (V_th) window, which is crucial for NAND operation. The energetic-trap distribution is a critical material property of the CTN that affects the V_th window between the erase and program V_th. An artificial neural network (ANN) was used to model the relationship between the energetic-trap distributions as an input parameter and the V_th window as an output parameter. A well-trained ANN was used with the gradient-descent method to determine the specific inputs that maximize the outputs. The trap densities (N_TD and N_TA) and their standard deviations (σ_TD and σ_TA) were found to most strongly impact the V_th window. As they increased, the V_th window increased because of the availability of a larger number of trap sites. Finally, when the ML-optimized energetic-trap distributions were simulated, the V_th window increased by 49% compared with the experimental value under the same bias condition. Therefore, the developed ML technique can be applied to optimize cell transistor processes by determining the material properties of the CTN in 3D NAND Flash.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.864-867
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• 2003

Since the development of semiconductors, various related research has been conducted. During research, silicon diodes have been commonly used because of their simplicity and low cost in the manufacturing process. This research deals with p-n junction threshold voltages from silicon diodes due to transport current at a cryogenic temperature. At a cryogenic temperature(77K) we could get minimum current which junction threshold voltage becomes constant. This is experimented on GPIB communication and it consist of programmable current source, multimeter which gauge the threshold voltage in a very low temperature caused by transport current from 5nA to 1mA and $LN_2$(77K) for coolant. This experiment is programmed all process using Measurement studio(Lab window) tool.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• Journal of IKEEE
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• v.23 no.4
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• pp.1224-1229
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• 2019

In this study, a liquid crystal (LC) cell was manufactured for smart window applications, such as blinds, and a system for controlling the light transmission rate was developed. The threshold voltage of the LC cell was 1.325 V and when the transmission rate was 10%, the voltage showed 2.370 V, indicating that the LC cell manufactured is driven at low voltage. The LC cell also operated reliably after being heated for 10 min at 80℃. with a response time of less than 30ms. The operation system designed the applied voltage of the LC cell with a interval of about 0.5 V from 0.15 V to 3.53 V and confirmed that the light transmission rate of the LC varies depending on the actual applied voltage. These results suggest that LC cells are likely to be smart window applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.994-999
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• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

• Applied Chemistry for Engineering
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• v.30 no.2
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• pp.205-211
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• 2019

Over the past several decades, the polymer dispersed liquid crystal (PDLC) has received particular attention as a material for developing smart window due to their electro-optical switchable properties. In this study, PDLC cells were fabricated using acrylate monomers, namely 2-hydroxyethyl acrylate (2-HEA) and ethylene glycol phenyl ether acrylate (EGPA), and the effect of the monomer composition on their electro-optical properties was investigated. The monomer mixture with a low viscosity (~10 cps) was easily filled between indium tin oxide (ITO) glasses by capillary action at room temperature. PDLC cells prepared using the mixture ratio of 1 : 9 (2-HEA : EGPA) did not show a complete opaque state at a 0 V condition but exhibited unstable electro-optical properties under an electric field. As the LC composition increased in the reaction mixture for PDLC cell preparation, the $V_{th}$ (threshold voltage) and $V_{sat}$ (saturation voltage) values as well as contrast ratio (CR) increased. $V_{th}$ and $V_{sat}$ values also increased with the cell gap thickness. PDLC cells with a $20{\mu}m$ cell gap thickness exhibited higher CR than those with 10 and $40{\mu}m$ cell gap thicknesses. Particularly, PDLC cells prepared using the mixture ratio of 7 : 3 (2-HEA : EGPA) showed excellent electro-optical properties such as a low driving voltage and high contrast ratio.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.324-326
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• 2016

In this study, we have investigated indium tin zinc oxide (ITZO) as an active channel for non-volatile memory (NVM) devices. The electrical and memory characteristics of NVM devices using multi-stack gate insulator SiO2/SiOx/SiOxNy (OOxOy) with Si-rich SiOx for charge storage layer were also reported. The transmittance of ITZO films reached over 85%. Besides, ITZO-based NVM devices showed good electrical properties such as high field effect mobility of 25.8 cm2/V.s, low threshold voltage of 0.75 V, low subthreshold slope of 0.23 V/dec and high on-off current ratio of $1.25{\times}107$. The transmission Fourier Transform Infrared spectroscopy of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000-2300 cm-1. It indicates that many silicon phases and defect sources exist in the matrix of the SiOx films. In addition, the characteristics of NVM device showed a retention exceeding 97% of threshold voltage shift after 104 s and greater than 94% after 10 years with low operating voltage of +11 V at only 1 ms programming duration time. Therefore, the NVM fabricated by high transparent ITZO active layer and OOxOy memory stack has been applied for the flexible memory system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.135-139
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• 2008

MFISFETs with platinum electrode on the $LiNbO_3$/aluminum nitride/Si(100) structures were successfully fabricated and the properties of the FETs have been discussed. $I_D-V_G$ characteristics of MFISFETs for linear region (that is, 0.1 V of the drain voltage) showed hysteresis loop with a counter-clockwise trace due to the ferroelectric nature of $LiNbO_3$ films. A memory window (i.e., threshold voltage shift) of the fabricated device was about 2[V] for a sweep from -4 to +4[V]. The estimated field-effect electron mobility and transconductance on a linear region were 530[$cm^2/V{\cdot}s$] and 0.16[mS/mm], respectively. The drain current of 27[${\mu}A$] on the "on" state was more than 3 orders of magnitude larger than that of 30[nA] on the "off" state at the same "read" gate voltage of l.5[V], which means the memory operation of the MFISFET.