• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1995년도 추계학술대회 논문집
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• pp.3-7
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• 1995

Force generated during grinding process causes elastic defomation. The effect of this deforms a workpiecs. So grinding system is explainable using the concept of macining elasticity phenomenon. Machining elasticity is defined as ratio between the true depth of c ut, and an importnat factor to affect material removal mchanism and productivity. Generally, to produce accurate surface and dimensionally precise components operators depend on their experiences. Because of these, productivity is reduced and time is wasted. The objective of this reserch is to study the effect of grinding conditions, such as table speed, depth of cut on the machining elasticity parameter.

• 진공이야기
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• 제3권1호
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• pp.16-21
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• 2016

FinFETs are able to be scaled down to 22 nm and beyond while suppressing effectively short channel effect, and have superior performance compared to 2-dimensional (2-D) MOSFETs. Bulk FinFETs are built on bulk Si wafers which have less defect density and lower cost than SOI(Silicon-On-Insulator) wafers. In contrast to SOI FinFETs, bulk FinFETs have no floating body effect and better heat transfer rate to the substrate while keeping nearly the same scalability. The bulk FinFET has been developed at 14 nm technology node, and applied in mass production of AP and CPU since 2015. In the development of the bulk FinFETs at 10 nm and beyond, self-heating effects (SHE) is becoming important. Accurate control of device geometry and threshold voltage between devices is also important. The random telegraph noise (RTN) would be problematic in scaled FinFET which has narrow fin width and small fin height.

• Advances in nano research
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• 제5권1호
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• pp.61-67
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• 2017

A semi-empirical approach to model the temperature effects on I-V characteristics of Carbon Nanotube Field Effect Transistors (CNTFETs) is proposed. The model includes two thermal parameters describing CNTFET behaviour in terms of saturation drain current and threshold voltage, whose values are extracted from the simulated and trans-characteristics of the device in different temperature conditions. Our results are compared with those of a numerical model online available, obtaining I-V characteristics comparable but with a lower CPU calculation time.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.19.2-19.2
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• 2011

ZnO nanowires have been fabricated by vapor-liquid-solidification with hot-walled pulsed laser deposition method. The diameter of ZnO nanowire has been systematically controlled simply by changing the thickness of Au catalyst. Field effect transistors with different diameter have been fabricated by using photolithography and e-beam lithography. The threshold voltage of ZnO nanowire FET showed enhanced mode and depleted mode depending on the diameter of ZnO nanowires. This is mainly due to the change of the carrier concentration depending on the size of nanowires. We have fabricated ZnO nanowire inverters using nanowire FETs. This simple method to fabricate ZnO nano-inverter will be useful to open the possibility of ZnO nanoelectronic applications.

• 한국결정성장학회지
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• 제5권4호
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• pp.408-413
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• 1995

초크랄스키 실리콘 기판의 뒷면에 형성된 기계적 손상이 레이저 여기/극초단파 반사 광전도 감쇠법에 의한 소수반송자 재결합 수명 측정에 미치는 영향을 고찰하였다. 기계적손상의 정도는 X-선 이중결정 회절법과 X-선 단면 측정법 및 습식산화/선택적 식각 방법으로 평가하였다. 그 결과, 웨이퍼 뒷면에 가해지는 기계적 손상의 세기가 강할수록 소수반송자 재결합 수명은 짧아지고, 소수반송자 재결합 수명 측정에 영향을 미치는 반치전폭의 임계값은 약13초임을 알 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.245-245
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• 2008

In this work, we describe the characterization of PVP films synthesized by spin-coater method and fabricate OTFTs of a bottom gate structure using pentacene as the active layer and polyvinylphenol (PVP) as the gate dielectric on Au gate electrode. We investigated the surface and electrical properties of PVP layer using an AFM method and MIM structure, and estimated the device properties of OTFTs including $I_D-V_D$, $I_D-V_G$, threshold voltage $V_T$, on/off ratio, and field effect mobility.

• Journal of Photoscience
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• 제3권3호
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• pp.127-132
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• 1996

Calcium has a variety of functions in neuron and muscle cells and blood clotting, especially in the visual system where dark adapted rods cotransport with Na$^+$ into the cell. An influx of Ca$^{2+}$ flows out of the cell through the Na$^+$ - Ca$^{2+}$ exchanger. By using a modified Ussing chamber in order to bring in vivo environment close, we have concluded that Ca$^{2+}$ blocks the activity of guanylate cyclase; in consequence, having an effect on the amplitude of electroretinogram (ERG). We suggest that Ca$^{2+}$ moves between the photoreceptor and the vitreous humor by way of certain Ca$^{2+}$ transport mechanisms. Also, the effect of Zn$^{2+}$ in Ca$^{2+}$ - free ringer solution caused an elevation of amplitude in ERG and a reduction of threshold.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.349-352
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• 1999

In this paper, we present simplified fault set which is made by analyzing fault relation to design specification in CMOS operational amplifier. The hard fault is easily modeled because an effect of hard fault is out of all design specification. However, the soft fault is not easily modeled because an effect of soft fault on design specification is varied according to position and depth of fault. We simulated hard and soft fault by HSPICE, varying threshold voltage and W/L ratio from 90% increase to 90% decrease. The decrease of test time and the production of high reliability mixed-mode IC are possible by the proposed fault set.

• 전자공학회논문지A
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• 제33A권6호
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• pp.189-196
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• 1996

We have studied sngle-frequency yield of 1.55${\mu}$m DFB lasers with uniform sinusoidal grating using an effective index transfer matrix method considering both threshold gain difference and spatial hole-burning effect. Optimum grating height and mirror reflectivities that maximize the single-frequency yield are found for a low-reflection (LR)/high-reflection(HR) mirror structure and a LR/as-cleaved miror structure for an assumed basic waveguide structure. LR/HR structure has a high yield of about 80% in a narrow range of grating height while LR/as-cleaved mirror structure has a low yield of about 50% in a relatively wide range of grating height. The effect of the low-reflection facet reflectivity is also studied.

• 반도체디스플레이기술학회지
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• 제14권2호
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.