• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9B
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• pp.1609-1617
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• 2000

In this paper a design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then subround is executed for one clock. To improve clock frequency online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. Also to eliminate performance degradation due to data input and data output time between host computer and coprocesor, background input/output method is used. The cryptographic coprocessor is designed using $0.25{\mu}{\textrm}{m}$ CMOS technology and consists of about 29,300 gates. Its peak performance is about 237 Mbps encryption or decryption rate under 100 Mhz clock frequncy and ECB mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2107-2115
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• 2007

In this paper, the scan conversion processor which converts the triangle represented by three vertices into pixel-level screen coordinates, depth coordinate, and color data is designed. The processor adopts scan-line algorithm which decomposes triangle into horizontal spans and then transforms the span into pixel data. By supporting top-left filling convention, it ensures that triangles that share an edge do not produce any dropouts or overlaps between adjacent polygons. It consists of about 21,400 gates and its maximum operating frequency is about 80 Mhz under 0.35um CMOS technology. Because its maximum pixel rate is about 80 Mpixels/sec, it can be applicable to mobile graphics application.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• Journal of the Korean Geographical Society
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• v.40 no.4 s.109
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• pp.416-427
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• 2005

This paper aims to investigate morphological changes of deltaic barrier islands in the Nakdong Estuary and especially their spatial variations after barrage construction. We analyzed shorelines, geometrical centroids, and areas to reveal the changes of barrier islands. Here, we suggest three interesting points from this study. First, each individual barrier island in the Nakdong estuary goes through a different stage of the geomorphic cycle. The frontal barrier islands such as Sinja-do and Doyo-deung grow because they are located in front of the gates of the barrage. Sediments in water out of the gates are moved to offshore and then reworked by coastal processes such as waves and tides. Second, on the contrary, Baekhap-deung located behind Doyo-deung now diminishes indicating that sediments mainly move to the frontal growing island. Third, there is no morphological change in several barrier islands far away from the main flow of the Nakdong river such as Jinwoo-do, Daema-deung, and Jangja-do. In conclusion, barrier islands in the Nakdong estuary show distinct spatial variations. As a barrier island is closer to the main channel or is in the frontal location, there happens a very dynamic change in the morphology of the island.

• Korean Journal of Ecology and Environment
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• v.50 no.1
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• pp.46-56
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• 2017

The Youngsan River estuary was physically changed by the construction of a sea embankment at near the mouth of estuary. Weirs were also constructed recently in the freshwater zone and it was reported that algal blooms occur more frequently. The freshwater introduced into saltwater zone from sluice gates of the embankment affects water quality but it has not been addressed that how the freshwater inputs influence the health of marine ecosystem. In this study, we used the data of water properties and phytoplankton communities collected at three stations for 4 days including before the freshwater discharge, during the discharge and after 1 and 2 days of discharge events. WQI(water quality index), TRIX (trophic status index) and P-IBI(phytoplankton index of biotic integrity) were used to evaluate the ecosystem health and long-term data were also utilized to determine the criteria for P-IBI. The results showed that grades of the ecosystem health assessed by the indices were low at the station near the gates and increased as downstream. However, the temporal pattern of grades was different depending on methods. Grades of WQI and TRIX decreased during the discharge and restored after the discharge whereas the grades of P-IBI decreased slightly even after the discharge. This suggests that P-IBI is more applicable to estuarine systems where experience extreme change of water properties than WQI and TRIX since P-IBI includes phytoplankton that can respond quickly to the change.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.14 no.2
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• pp.136-150
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• 2002

To improve the water quality of the recently constructed Siwhaho, sluice gates were operated to allow free exchange of water with the sea. This estuarine lake connected to the outer sea through narrow gates is affected mainly by flushing by gate operation and river flows and wind forcing sometimes. As a predicting tool far the water qualities, a three-dimensional finite volume model CE-QUAL-ICM is incorporated into a finite element hydrodynamic model, TIDE3D. In coupling these two different modules, a new error minimization technique is applied by considering conservation of mass. Model tests for one year after calibration and validation using field observation show that eutrophication and other biological changes reach quasi-steady state after initial 60 days of simulation, thus it would be necessary to consider moderate ramp up option to remove initial uncertainties due to cold start option. Sediment-water interaction might not be a concern in the long-term simulation, since its effect is negligible. Simulated results show the newly applied scheme can be applied with satisfaction not only fur lessening of eutrophic processes in an estuarine lake but also looking for some active circulation to improve water quality.

• Journal of Construction Engineering and Project Management
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• v.8 no.4
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• pp.1-24
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• 2018

In the last decade, the use of Building Information Modeling (BIM) as a new technology has been applied with traditional Computer-aided design implementations in an increasing number of architecture, engineering, and construction projects and applications. Its employment alongside construction management, can be a valuable tool in helping move these activities and projects forward in a more efficient and time-effective manner. The traditional stakeholders, i.e., Owner, A/E and the Contractor are involved in this BIM system that is used in almost every activity of construction projects, such as design, cost estimate and scheduling. This article extracts major features of the application of BIM from perspective of participating BIM components, along with the different phrases, and applies to them a logistic analysis using a fuzzy performance tree, quantifying these phrases to judge the effectiveness of the BIM techniques employed. That is to say, these fuzzy performance trees with fuzzy logic concepts can properly translate the linguistic rating into numeric expressions, and are thus employed in evaluating the influence of BIM applications as a mathematical process. The rotational fuzzy models are used to represent the membership functions of the performance values and their corresponding weights. Illustrations of the use of this fuzzy BIM performance tree are presented in the study for the uninitiated users. The results of these processes are an evaluation of BIM project performance as highly positive. The quantification of the performance ratings for the individual factors is a significant contributor to this assessment, capable of parsing vernacular language into numerical data for a more accurate and precise use in performance analysis. It is hoped that fuzzy performance trees and fuzzy set analysis can be used as a tool for the quality and risk analysis for other construction techniques in the future. Baldwin's rotational models are used to represent the membership functions of the fuzzy sets. Three scenarios are presented using fuzzy MEAN, AND and OR gates from the lowest to intermediate levels of the tree, and fuzzy SUM gate to relate the intermediate level to the top component of the tree, i.e., BIM application final performance. The use of fuzzy MEAN for lower levels and fuzzy SUM gates to reach the top level suggests the most realistic and accurate results. The methodology (fuzzy performance tree) described in this paper is appropriate to implement in today's construction industry when limited objective data is presented and it is heavily relied on experts' subjective judgment.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.907-916
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• 2019

In this paper, we propose a new five-qubit multiple bit flip code that can completely protect the target qubit from all multiple bit flip errors using only CNOT gates. The proposed multiple bit flip codes can be easily extended to multiple phase flip codes by embedding Hadamard gate pairs in the root error section as in conventional single bit flip code. The multiple bit flip code and multiple phase flip code in this paper share the state vector error information by four auxiliary qubits. These four-qubit state vectors reflect the characteristic that all the multiple flip errors with Pauli X and Z corrections commonly include a specific root error. Using this feature, this paper shows that low-cost implementation is possible despite the QECC design for multiple-flip error correction by batch processing the detection and correction of Pauli X and Z root errors with only three CNOT gates. The five-qubit multiple bit flip code and multiple phase flip code proposed in this paper have 100% error correction rate and 50% error discrimination rate. All QECCs presented in this paper were verified using QCAD simulator.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.