• Title/Summary/Keyword: thin-film type

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Microcrystalline Silicon Thin-film(${\mu}c$-Si:H) and Solar Cells prepared at Low Temperature by 60MHz PECVD (60MHz PECVD법에 의한 ${\mu}c$-Si:H 박막의 저온증착 및 태양전지 응용)

  • Lee, J.C.;Chung, Y.S.;Kim, S.K.;Yoon, K.H.;Song, J.;Park, I.J.;Kwon, S.W.;Lim, K.S.
    • Proceedings of the KIEE Conference
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    • 2003.07c
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    • pp.1595-1597
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    • 2003
  • This paper presents the deposition of ${\mu}c$-Si:H thin-film and fabrication of a solar cell by VHF-PECVD method. The ${\mu}c$-Si:H thin films and pin-type solar cells are fabricated using multi-chamber cluster tool system. A 7.4% conversion efficiency was achieved from ${\mu}c$-Si:H thin film solar cells with total thickness less than $5{\mu}m$. The physical characteristic was measured by Raman spectroscopy, Solar cell characteristic was measured under AM1.5 illumination.

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Amorphous silicon thin-film solar cells with high open circuit voltage by using textured ZnO:Al front TCO (ZnO:Al 투명전도막을 이용한 높은 개방전압을 갖는 비정질 실리콘 박막 태양전지 제조)

  • Lee, Jeong-Chul;Dutta, Viresh;Yi, Jun-Sin;Song, Jin-Soo;Yoon, Kyung-Hoon
    • 한국신재생에너지학회:학술대회논문집
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    • 2006.06a
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    • pp.158-161
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    • 2006
  • Superstrate pin amorphous silicon thin-film (a-Si:H) solar cells are prepared on $SnO_2:F$ and ZnO:Al transparent conducting oxides (TCO) In order to see the effect of TCO/P-layers on a-Si:H solar cell operation. The solar cells prepared on textured ZnO:Al have higher open circuit voltage $V_{oc}$ than cells prepared on $SnO_2:F$. Presence of thin microcrystalline p-type silicon layer $({\mu}c-Si:H)$ between ZnO:Al and p a-SiC:H plays a major role by causing improvement in fill factor as well as $V_{oc}$, of a-Si:H solar cells prepared on ZnO:Al TCO. Without any treatment of pi interface, we could obtain high $V_{oc}$, of 994mv while keeping fill factor (72.7%) and short circuit current density $J_{sc}$ at the same level as for the cells on $SnO_2:F$ TCO. This high $V_{oc}$ value can be attributed to modification in the current transport in this region due to creation of a potential barrier.

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CO2 Gas Responsibility of SnO5 Thin Film Depending on the Annealing Temperature (SnO2 박막의 열처리 온도에 따른 CO2가스 반응성)

  • Oh, Teresa
    • Journal of the Semiconductor & Display Technology
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    • v.16 no.4
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    • pp.75-78
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    • 2017
  • The $CO_2$ gas responsibility of $SnO_2$ thin films was researched with various annealing temperatures. $SnO_2$ was prepared on n-type Si substrate by RF magnetron sputtering system and annealed in a vacuum condition. The bonding structure of $SnO_2$ was changed from amorphous to crystal structure with increasing the annealing temperature, and the content of oxygen vacancy was researched the highest of the annealed at $60^{\circ}C$. The $SnO_2$ annealed at $60^{\circ}C$ had the characteristics of the highest capacitance. The special properties of $CO_2$ gas responsibility was found at the $SnO_2$ thin film annealed at $60^{\circ}C$ with amorphous structure because of the combination with the oxygen vacancies and $CO_2$ gases changed the resistivity. The amorphous structure enhanced the responsibility at the $SnO_2$ surface and the conductivity of $SnO_2$ thin film.

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Detection of Blood Agent Gas Using $SnO_2$ Thin Film Gas Sensor

  • Choi, Nak-Jin;Kwak, Jun-Hyuk;Lim, Yeon-Tae;Joo, Byung-Su;Lee, Duk-Dong;Bahn, Tae-Hyun
    • Journal of Korean Society for Atmospheric Environment
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    • v.20 no.E2
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    • pp.69-75
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    • 2004
  • In this study, thin film gas sensor based on tin oxide was fabricated to examine its characteristics. Target gas is acetonitrile ($CH_3$CN) which is a blood simulant for the chemical warfare agent. Sensing materials are SnO$_2$ SnO$_2$/Pt, and Sn/Pt with thickness from 1000 to 3000 $\AA$. The sensor consists of a sensing electrode with inter-digit (IDT) type in front side and a heater in rear side. Resistance changes of sensing materials are monitored on real time basis using a data acquisition board with a 12-bit analog to digital converter. Sensitivities are measured at different operating temperatures also with different gas concentrations and film thickness. The high sensitivity is obtained for Sn (3000 $\AA$)/Pt (30 $\AA$) at 30$0^{\circ}C$ for 3 ppm. Response and recovery times were about 40 and 160 s, respectively. Repetition measurements showed very good results with $\pm$3% in full scale range.

Epitaxial growth of yttrium-stabilized HfO$_2$ high-k gate dielectric thin films on Si

  • Dai, J.Y.;Lee, P.F.;Wong, K.H.;Chan, H.L.W.;Choy, C.L.
    • Electrical & Electronic Materials
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    • v.16 no.9
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    • pp.63.2-64
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    • 2003
  • Epitaxial yttrium-stabilized HfO$_2$ thin films were deposited on p-type (100) Si substrates by pulsed laser deposition at a relatively lower substrate temperature of 550. Transmission electron microscopy observation revealed a fixed orientation relationship between the epitaxial film and Si; that is, (100)Si.(100)HfO$_2$ and [001]Si/[001]HfO$_2$. The film/Si interface is not atomically flat, suggesting possible interfacial reaction and diffusion, X-ray photoelectron spectrum analysis also revealed the interfacial reaction and diffusion evidenced by Hf silicate and Hf-Si bond formation at the interface. The epitaxial growth of the yttrium stabilized HfO$_2$ thin film on bare Si is via a direct growth mechanism without involoving the reaction between Hf atoms and SiO$_2$ layer. High-frequency capacitance-voltage measurement on an as-grown 40-A yttrium-stabilized HfO$_2$ epitaxial film yielded an dielectric constant of about 14 and equivalent oxide thickness to SiO$_2$ of 12 A. The leakage current density is 7.0${\times}$ 10e-2 A/$\textrm{cm}^2$ at 1V gate bias voltage.

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The Effect of Thernal Annealing and Growth of $CdIn_2S_4$ Single Crystal Thin Film by Hot Wall Epitaxy (Hot Wall Epitaxy(HWE)법에 의해 성장된 $CdIn_2S_4$ 단결정 박막 성장의 광학적 특성)

  • Yun, Seok-Jin;Hong, Kwang-Joon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.11a
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    • pp.129-130
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    • 2006
  • A stoichiometric mixture of evaporating materials for $CdIn_2S_4$ single crystal thin films was prepared from horizontal furnace. To obtain the single crystal thin films, $CdIn_2S_4$ mixed crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by hot wall epitaxy(HWE) system. The source and substrate temperatures were $630^{\circ}C$ and $420^{\circ}C$, respectively. After the as-grown $CdIn_2S_4$ single crystal thin films was annealed in Cd-, S-, and In-atmospheres, the origin of point defects of $CdIn_2S_4$ single crystal thin films has been investigated by the photoluminescence(PL) at 10 K. The native defects of $V_{cd}$, $V_s$, $Cd_{int}$, and $S_{int}$, obtained by PL measurements were classified as a donors or acceptors type. And we concluded that the heat-treatment m the S-atmosphere converted $CdIn_2S_4$ single crystal thin films to an optical p-type. Also. we confirmed that In in $CdIn_2S_4$/GaAs did not form the native defects because In in $CdIn_2S_4$ single crystal thin films existed in the form of stable bonds.

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Growth and Effect of Thermal Annealing for CuInse2 Single Crystal Thin Film by Hot Wall Epitaxy (Hot Wall Epitaxy (HWE)법에 의한 CuInse2 단결정 박막 성장과 열처리 효과)

  • Lee Gyungou;Hong Kwangjoon
    • Korean Journal of Materials Research
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    • v.14 no.11
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    • pp.755-763
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    • 2004
  • A stoichiometric mixture of evaporating materials for $CuInse_2$ single crystal thin films was prepared from horizontal electric furnace. To obtain the single crystal thin films, $CuInse_2$ mixed crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by the hot wall epitaxy (HWE) system. The source and substrate temperatures were $620^{\circ}C\;and\;410^{\circ}C$, respectively. The temperature dependence of the energy band gap of the $CuInse_2$ obtained from the absorption spectra was well described by the Varshni's relation, $E_{g}(T)=1.1851 eV - (8.99{\times}10^{-4} eV/K)T^2/(T+153 K)$. After the aa-grown $CuInse_2$ single crystal thin films was annealed in Cu-, Se-, and In-atmospheres, the origin of point defects of $CuInse_2$ single crystal thin films has been investigated by the photoluminescence(PL) at 10 K. The native defects of $V_{cu},\;V_{Se},\;Cu_{int},\;and\;Se_{int}$ obtained by PL measurements were classified as a donors or accepters type. And we concluded that the heat-treatment in the Cu-atmosphere converted $CuInse_2$ single crystal thin films to an optical n-type. Also, we confirmed that In in $CuInse_2$/GaAs did not form the native defects because In in $CuInse_2$ single crystal thin films existed in the form of stable bonds.

Liquid Crystal Alignment Effect of Flexible Liquid Crystal Display with Low Temperature Alignment Layer (저온배향막을 이용한 Flexible 액정디스플레이의 액정 배향 효과)

  • Hwang, Jeoung-Yeon;Nam, Ki-Hyung;Kim, Jong-Hwan;Kim, Kang-Woo;Seo, Dae-Shik;Suh, Dong-Hack
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.199-202
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    • 2003
  • We have investigated the generation of pretilt angle for a nematic liquid crystal (NLC) alignment with rubbing alignment method on two kinds of polyimide (PI) surfaces using thin plastic substrates. The generated NLC pretilt angles on the pre-imidized type PI are about $3.8^{\circ}$ by the rubbing alignment method with thin plastic substrates, However, the pretilt angle measured at about $2.8^{\circ}$ lower on the polyamic acid type PI than by pre-imidized type PI surface with thin polymer film. The tilt angle increases as increasing curring temperature for making polyimide layer using polyamic acid type PI. It was concluded that pretilt angle in the polyimide surface is attributable to the increasing of imide rato.

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용액공정을 이용한 SiOC/SiO2 박막제조

  • Kim, Yeong-Hui;Kim, Su-Ryong;Gwon, U-Taek;Lee, Jeong-Hyeon;Yu, Yong-Hyeon;Kim, Hyeong-Sun
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2009.11a
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    • pp.36.2-36.2
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    • 2009
  • Low dielectric materials have been great attention in the semiconductor industry to develop high performance interlayer dielectrics with low k for Cu interconnect technology. In our study, the dielectric properties of SiOC /SiO2 thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. Polyphenylcarbosilane was synthesized from thermal rearrangement of polymethylphenylsilane around $350^{\circ}C{\sim}430^{\circ}C$. Characterization of synthesized polyphenylcarbosilane was performed with 29Si, 13C, 1H NMR, FT-IR, TG, XRD, GPC and GC analysis. From FT-IR data, the band at 1035 cm-1 is very strong and assigned to CH2 bending vibration in Si-CH2-Si group, indicating the formation of the polyphenylcarbosilane. Number average of molecular weight (Mn) of the polyphenylcarbosilane synthesized at $400^{\circ}C$ for 6hwas 2, 500 and is easily soluble in organic solvent. SiOC/SiO2 thin film was fabricated on ton-type silicon wafer by spin coating using 30wt % polyphenylcarbosilane incyclohexane. Curing of the film was performed in the air up to $400^{\circ}C$ for 2h. The thickness of the film is ranged from $1{\mu}m$ to $1.7{\mu}m$. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and show a dielectric constant as low as 2.5 without added porosity. The SiOC /SiO2 thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.

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Dependence of Self-heating Effect on Width/Length Dimension in p-type Polycrystalline Silicon Thin Film Transistors

  • Lee, Seok-Woo;Kim, Young-Joo;Park, Soo-Jeong;Kang, Ho-Chul;Kim, Chang-Yeon;Kim, Chang-Dong;Chung, In-Jae
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.505-508
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    • 2006
  • Self-heating induced device degradation and its width/length (W/L) dimension dependence were studied in p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs). Negative channel conductance was observed under high power region of output curve, which was mainly caused by hole trapping into gate oxide and also by trap state generation by self-heating effect. Self-heating effect became aggravated as W/L ratio was increased, which was understood by the differences in heat dissipation capability. By reducing applied power density normalized to TFT area, self-heating induced degradation could be reduced.

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