• 센서학회지
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• 제29권4호
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• pp.266-269
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• 2020

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In_0.7Ga_0.3As quantum-well (QW) metal-oxide-semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In_0.7Ga_0.3As QW MOSFETs with and without (NH₄)₂S treatment and then deposited 1/4 nm of Al₂O₃/HfO₂ through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density D_it (2.83×10¹² cm^-2eV^-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.56-60
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• 2000

Cube texture를 갖는 Ni기판위에 MOCVD(Metal Chemical Vapor Deposition)를 이용하여 NiO, CeO$_2$, YBCO 박막을 제조하였다. NiO(200)와 CeO$_2$(200) buffer layer는 450${\sim}$470$^{\circ}$C에서 10분간 MOCVD방법으로 (100)<001>Ni 기판위에 직접 증착하였다. 제조된 NiO, CeO$_2$ buffer layer는 조직이 치밀하며 표면의 상태가 매우 좋으며 Ni기판 위에 epitaxial하게 성장하였다. NiO는 Ni기판과 NiO<100>//Ni<100>의 방위관계를 가지고 성장하였으며, CeO$_2$는 증착조건에 따라 CeO$_2$ <100>//Ni<100> 및 CeO$_2$ <110>//Ni<100> 의 방위관계를 가지고 성장하였다. 증착된 NiO막과 CeO$_2$막에서 균열은 발생하지 않았다. MOCVD법으로 표면에 biaxial texture를 갖는 ceramic buffer를 증착시킨 NiO/Ni및 CeO$_2$/Ni 기판위에 YBCO박막을 MOCVD법으로 제조하였다. YBCO막은 기판온도 800$^{\circ}$C,증착압력 10torr, 산소분압을 0.7torr로 하여 10분간 행하였다. 공급원료의 조성에 따라 YBCO의 막의 texture와 형성되는 상이 변화되었다. NiO/Ni및 CeO$_2$/Ni 기판 위에 증착된 YBCO막은 c축 배향성을 가지고 성장하였으며, -scan 및 ${\varphi}$ -scan으로 측정한 (500)면의 in-plane과 (110)면의 out-of-plane의 FWHM(Full Width Half Maximum)값은 각각 10$^{\circ}$ 미만으로 우수하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.361.2-361.2
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• 2014

Transition metal dichalcogenides (MoS2, WS2, WSe2, MoSe2, NbS2, NbSe2, etc.) are layered materials that can exhibit semiconducting, metallic and even superconducting behavior. In the bulk form, the semiconducting phases (MoS2, WS2, WSe2, MoSe2) have an indirect band gap. Recently, these layered systems have attracted a great deal of attention mainly due to their complementary electronic properties when compared to other two-dimensional materials, such as graphene (a semimetal) and boron nitride (an insulator). However, these bulk properties could be significantly modified when the system becomes mono-layered; the indirect band gap becomes direct. Such changes in the band structure when reducing the thickness of a WS2 film have important implications for the development of novel applications, such as valleytronics. In this work, we report for the controlled synthesis of large-area (~cm2) single-, bi-, and few-layer WS2 using a two-step process. WOx thin films were deposited onto a Si/SiO2 substrate, and these films were then sulfurized under vacuum in a second step occurring at high temperatures ($750^{\circ}C$). Furthermore, we have developed an efficient route to transfer these WS2 films onto different substrates, using concentrated HF. WS2 films of different thicknesses have been analyzed by optical microscopy, Raman spectroscopy, and high-resolution transmission electron microscopy.

• 한국진공학회지
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• 제17권2호
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• pp.109-112
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• 2008

고집적화된 반도체 소자 기술은 나날이 발전하고 있다. 특히 금속 배선을 위한 박막제조 공정에서 배선 선폭은 감소하고 있으며, 그 길이는 더욱 증가하게 되었다. 이러한 상황에서 금속 배선 물질에 대한 연구가 진행 되었고 그 결과 Cu가 그 대안으로 인식되었다. 하지만 Cu는 저온에서도 Si기판과 반응하므로 인하여 접촉면의 저항이 급격히 증가하여 소자로써의 기능이 불가능하게 되는 단점이 있다. 따라서 이러한 Cu와 Si기판 사이의 반응을 효과적으로 방지할 확산방지막의 개발이 필수 요건이 되었다. 본 연구는 Cu의 확산을 방지하는 W-C-N 확산방지막에 대한 연구로 질소비율과 열처리 온도를 변화하여 실험하였으며, 특히 격자상수 변화를 통하여 W-C-N 확산방지의 특성에 대하여 연구하였다.

• 한국재료학회지
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• 제23권3호
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• pp.183-189
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• 2013

$Cu_2ZnSn(S,Se)_4$ material is receiving an increased amount of attention for solar cell applications as an absorber layer because it consists of inexpensive and abundant materials (Zn and Sn) instead of the expensive and rare materials (In and Ga) in $Cu(In,Ga)Se_2$ solar cells. We were able to achieve a cell conversion efficiency to 4.7% by the selenization of a stacked metal precursor with the Cu/(Zn + Sn)/Mo/glass structure. However, the selenization of the metal precursor results in large voids at the absorber/Mo interface because metals diffuse out through the top CZTSe layer. To avoid the voids at the absorber/Mo interface, binary selenide compounds of ZnSe and $SnSe_2$ were employed as a precursor instead of Zn and Sn metals. It was found that the precursor with Cu/$SnSe_2$/ZnSe stack provided a uniform film with larger grains compared to that with $Cu_2Se/SnSe_2$/ZnSe stack. Also, voids were not observed at the $Cu_2ZnSnSe_4$/Mo interface. A severe loss of Sn was observed after a high-temperature annealing process, suggesting that selenization in this case should be performed in a closed system with a uniform temperature in a $SnSe_2$ environment. However, in the experiments, Cu top-layer stack had more of an effect on reducing Sn loss compared to $Cu_2Se$ top-layer stack.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• 대한전자공학회논문지SD
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• 제40권1호
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• pp.1-10
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• 2003

본 연구에서는 Metal-Ferroelecric-Semiconductor FET (MFSFET) 소자의 특성을 시뮬레이션 하였다. 시뮬레이션에서는 field-dependent polarization 모델과 square-law FET 모델이 도입되었다. MFSFET 시뮬레이전에서 C-V/sub G/ 곡선은 축적과 공핍 및 반전 영역을 확실하게 나타내었다. 게이트 전압에 따른 캐패시턴스, subthreshold 전류 그리고, 드레인 전류특성에서 강유전체 항전압이 0.5, 1V 일 때, 각각 1, 2V 의 memory window 를 나타내었다. 드레인 전류-드레인 전압 곡선은 증가영역과 포화영역으로 구성되었다. 드레인 전류-드레인 전압 곡선에서 두 부분의 문턱전압에 의해 나타난 포화드레인 전류차이는 게이트 전압이 0, 0.1, 0.2 그리고, 0.3V 일 때, 각각 1.5, 2.7, 4.0 그리고 5.7㎃ 이었다. 시간경과 후의 드레인 전류를 분석하였는데, PLZT(10/30/70) 박막은 10년 후에 약 18%의 포화 전류가 감소하여 우수한 신뢰성을 보였다. 본 모델은 MFSFET 소자의 동작을 예측하는데 중요한 역할을 할 것으로 판단된다.

• E2M - 전기 전자와 첨단 소재
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• 제9권1호
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• 한국전기전자재료학회논문지
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• 제17권11호
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• pp.1241-1245
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• 2004

Continuous physical vapor deposition (PVD) method is one of many processes to fabricate long length coated conductor which is required for successful large-scale application of superconducting power devices. Three film deposition systems (pulsed laser deposition, sputtering, and evaporation) equipped with reel-to-reel(R2R) metal tape moving apparatus were installed and used to deposit multi-layer oxide thin films. Both RABiTS and IBAD texture templates are used. IBAD template consists of CeO$_2$(PLD)/YSZ(IBAD) on stainless steel(SS) metal tape, and RABiTS template has the structure of CeO$_2$/YSZ/Y$_2$O$_3$ which was continuously deposited on Ni-alloy tape using R$_2$R evaporation and DC reactive sputtering in a deposition system designed to do both processes. 0.4 m-long coated conductor with Ic(77 K) of 34 A/cm was fabricated using RABiTS template. 0.5 m and 1.1 m-long coated conductor with Ic(77 K) of 41 A/cm and 26 A/cm were fabricated using IBAD template.

• 한국정보통신학회논문지
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• 제12권3호
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• pp.534-540
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• 2008

본 연구에서는 MFSFET (Metal-Ferroelectric-Semiconductor FET) 소자의 모델링을 바탕으로 적응형 학습회로를 설계하고, 그 수치적인 결과를 분석하였다. 적응형 학습회로에서 출력주파수는 MFSFET 소자의 소스-드레인 저항과 캐패시턴스에 반비례하는 특성을 보여주었다. Short pulse 수에 따른 포화드레인 전류곡선은 강유전체의 분극반전 특성과 유사함을 확인할 수 있었고, 이는 강유전체 분극이 MFSFET 소자의 드레인 전류조절에 핵심적인 요소로 작용한다는 사실을 의미한다. 다음으로 MFSFET 소자의 소스-드레인 저항으로부터 dimensionality factor와 적응형 학습회로의 펄스 수에 따른 출력주파수 변화를 분석하였다. 이 특성으로부터 입력펄스의 진행에 따라 출력펄스의 점진적인 주파수 변화를 의미하는 적응형 학습 특성을 명확하게 확인할 수 있었고, 미래 뉴럴 네트워크에서 본 회로가 뉴런의 시넵스 부분에 효과적으로 사용될 수 있음을 입증하였다.