• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.1105-1108
• /
• 2003

In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.

• 전자공학회논문지A
• /
• 제32A권12호
• /
• pp.122-129
• /
• 1995

The most important feature of a-Si TFT is dense localized states such as dangling bonds which exist in tis bandgap. Electrons trapped by localized states dominate the potential distribution in the active a-Si region ,and influence the performance of a-Si TFT. In this paper, we describe the electrical characteristics of a-Si TFT with respect to trap distribution within bandgap, electron mobility and interface states using 2-Dimensional device simulator and compare the result of simulation with measurements. Using the mixed-mode simulator, we can predict the potential variation of pixel which causes residual image problem during the turn-off of a-Si TFT driving circuit. Therefore it is possible to consider trade-off between potential variation of pixel and turn-on current of a-Si TFT for the optimized driving circuit.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
• /
• pp.1564-1567
• /
• 2005

Zinc oxide thin films were grown at the t emperature of $100^{\circ}C$ and $150^{\circ}C$ by means of plasma enhanced atomic layer deposition (PEALD) and conventional atomic layer deposition for applying to the transparent thin film transistor (TTFT). The growth rate of $1.9{\AA}/cycle$ with oxygen plasma is similar to that of film grown with water. While the sheet resistivity of ZnO grown with water is 1233 ohm/sq, that of film grown with oxygen plasma was too high to measure with 4 point probe and hall measurement system. The resistivity of the films grown with oxygen plasma estimated to be $10^6$ times larger than that of the films grown with water. The difference of electrical property between two films was caused by the O/Zn atomic ratio. We fabricated ZnO-TFT by means of ALD for the first time and the ZnO channel fabricated with water showed saturation mobility of $0.398cm^2/V{\cdot}s$ with bottom gate configuration.

• 반도체디스플레이기술학회지
• /
• 제13권1호
• /
• pp.43-49
• /
• 2014

Zinc-tin oxides (ZTO) thin film transistors have been fabricated at different process pressure via re sputtering technique. TFT properties were improved by depositing channel layers at lower pressure. From the analysis of TFTs comprised of multi layer channel, deposited consecutively at different sputtering pressure, it was suggested that the electrical characteristics of TFTs were mainly affected by interfacial layer due to their high conductance, however, the stability under the NBIS condition was influenced by whole bulk layer due to low concentration of positive charges, which might be generated by the oxygen vacancy transition, from Vo0 to $Vo^{2+}$. Those improvements were attributed to increasing sputtered target atoms and decreasing harmful effects of oxygen molecules by adopting low sputtering pressure condition.

• ETRI Journal
• /
• 제31권6호
• /
• pp.653-659
• /
• 2009

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al-doped zinc tin oxide (AZTO) TFT. Deposition of an ultra-thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo-resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.

• 대한전자공학회논문지SD
• /
• 제37권12호
• /
• pp.29-34
• /
• 2000

금속유도 측면 결정화에 의해 제작된 다결정 실리콘 박막 트랜지스터(Thin Film Transistor; TFT)의 전기적 스트레스의 효과에 대해 연구하였다. MILC로 제작된 TFT에 전기적 스트레스가 인가될 때, off-state 전류가 100배에서 10000배까지 감소한다. 그러나 전기적 스트레스를 인가한 소자를 관상로에서 열처리를 할 경우 열처리온도가 증가할 수록 off-state 전류가 다시 증가했다. 열처리온도에 따른 off-state 전류의 의존성으로부터 MILC 다결정 실리콘 박막내 트랩준위의 활성화에너지(0.34eV)를 얻어냈다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
• /
• pp.258-258
• /
• 2016

최근 디스플레이 산업의 발전에 따라 고성능 디스플레이가 요구되며, 디스플레이의 백플레인 (backplane) TFT (thin film transistor) 구동속도를 증가시키기 위한 연구가 활발히 진행되고 있다. 트랜지스터의 구동속도를 증가시키기 위해 높은 이동도는 중요한 요소 중 하나이다. 그러나, 기존 백플레인 TFT에 주로 사용된 amorphous silicon (a-Si)은 대면적화가 용이하며 가격이 저렴하지만, 이동도가 낮다는 (< $1cm2/V{\cdot}s$) 단점이 있다. 따라서 전기적 특성이 우수한 산화물 반도체가 기존의 a-Si의 대체 물질로써 각광받고 있다. 산화물 반도체는 비정질 상태임에도 불구하고 a-Si에 비해 이동도 (> $10cm2/V{\cdot}s$)가 높고, 가시광 영역에서 투명하며 저온에서 공정이 가능하다는 장점이 있다. 하지만, 차세대 디스플레이 백플레인에서는 더 높은 이동도 (> $30cm2/V{\cdot}s$)를 가지는 TFT가 요구된다. 따라서, 본 연구에서는 차세대 디스플레이에서 요구되는 높은 이동도를 갖는 TFT를 제작하기 위하여, amorphous In-Ga-Zn-O (a-IGZO) 채널하부에 화학적으로 안정하고 전도성이 뛰어난 SnO2 채널을 얇게 형성하여 TFT를 제작하였다. 표준 RCA 세정을 통하여 p-type Si 기판을 세정한 후, 열산화 공정을 거쳐서 두께 100 nm의 SiO2 게이트 절연막을 형성하였다. 본 연구에서 제안된 적층된 채널을 형성하기 위하여 5 nm 두계의 SnO2 층을 RF 스퍼터를 이용하여 증착하였으며, 순차적으로 a-IGZO 층을 65 nm의 두께로 증착하였다. 그 후, 소스/드레인 영역은 e-beam evaporator를 이용하여 Ti와 Al을 각각 5 nm와 120 nm의 두께로 증착하였다. 후속 열처리는 퍼니스로 N2 분위기에서 $600^{\circ}C$의 온도로 30 분 동안 실시하였다. 제작된 소자에 대하여 TFT의 전달 및 출력 특성을 비교한 결과, SnO2 층을 형성한 TFT에서 더 뛰어난 전달 및 출력 특성을 나타내었으며 이동도는 $8.7cm2/V{\cdot}s$에서 $70cm2/V{\cdot}s$로 크게 향상되는 것을 확인하였다. 결과적으로, 채널층 하부에 SnO2 층을 형성하는 방법은 추후 높은 이동도를 요구하는 디스플레이 백플레인 TFT 제작에 적용이 가능할 것으로 기대된다.

• 한국응용과학기술학회지
• /
• 제30권2호
• /
• pp.290-296
• /
• 2013

We analysed interfacial traps in organic thin-film transistors (TFTs) in which pentacene and 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) organic semiconductors were deposited by means of vacuum-thermal evaporation and drop-coating methods, respectively. The thermally-deposited pentacene film consists of dentritic grains with the average grain size of around 1 m, while plate-like crystals over a few hundred microns are observed in the solution-processed TIPS-pentacene film. From the transfer characteristics of both TFTs, lower subthreshold slope of 1.02 V/decade was obtained in the TIPS-pentacene TFT, compared to that (2.63 V/decade) of the pentacene transistor. The interfacial trap density values calculated from the subthreshold slope are about $3.4{\times}10^{12}/cm^2$ and $9.4{\times}10^{12}/cm^2$ for the TIPS-pentacene and pentacene TFTs, respectively. Herein, lower subthreshold slope and less interfacial traps in TIPS-pentacene TFTs are attributed to less domain boundaries in the solution-processed TIPS-pentacene film.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
• /
• pp.737-739
• /
• 1998

Gate insulators using various fluoride films were investigated for thin film transistor applications. Conventional oxide containing materials exhibited high interface states, high $D_{it}$ gives an increased threshold voltage and poor stability of TFT. To improve TFT performances, we must reduce interface trap charge density between Si and gate insulator. In this paper, we investigated gate insulators such as such as $CaF_2$, $SrF_2$, $MgF_2$ and $BaF_2$. These materials exhibited an improvement in lattice mismatch, difference in thermal expansion coefficient, and electrical stability MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 0.737%, breakdown electric field higher than 1.7MV/cm and leakage current density of $10^{-6}A/cm^2$. This paper probes a possibility of new gate insulator material for TFT application.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
• /
• pp.305-308
• /
• 2004

We present a novel process for the ultra low temperature (<150$^{\circ}C$) polycrystalline silicon (ULTPS) TFT for the flexible display applications on the plastic substrate. The sequential lateral solidification (SLS) was used for the crystallization of the amorphous silicon film deposited by rf magnetron sputtering, resulting in high mobility polycrystalline silicon (poly-Si) film. The gate dielectric was composed of thin $SiO_2$ formed by plasma oxidation and $Al_2O_3$ deposited by plasma enhanced atomic layer deposition. The breakdown field of gate dielectric on poly-Si film showed above 6.3 MV/cm. Laser activation reduced the source/drain resistance below 200 ${\Omega}$/ㅁ for n layer and 400 ${\Omega}$/ㅁ for p layer. The fabricated ULTPS TFT shows excellent performance with mobilities of 114 $cm^2$/Vs (nMOS) and 42 $cm^2$/Vs (pMOS), on/off current ratios of 4.20${\times}10^6$ (nMOS) and 5.7${\times}10^5$ (PMOS).