• Title/Summary/Keyword: thin film transistor (TFT)

Search Result 502, Processing Time 0.03 seconds

A Study of Master Production Scheduling Scheme in TFT-LCD Factory considering Line Balancing (TFT-LCD 공장의 라인 밸런싱을 고려한 MPS 수립에 관한 연구)

  • Won, Dae-Il;Baek, Jong-Kwan;Kim, Sung-Shick
    • IE interfaces
    • /
    • v.16 no.4
    • /
    • pp.463-472
    • /
    • 2003
  • In this study we consider the problem of MPS(master production planning) of TFT-LCD(Thin Film Transistor - Liquid Crystal Display) production factory. Due to the complexities of the TFT-LCD production processes, it is difficult to build effective MPS. This study presents an algorithm having a concept of IDPQ(Ideal Daily Production Quantity) that considers line balancing of TFT-LCD production process. In general, the MPS building procedure does not consider line balancing in non-bottleneck processes. MPS without considering line balancing may make ineffective schedule. We present algorithms for building MPS considering factory capacity and line balancing according to the sales order.

Effect of drain bias stress on the stability of nanocrystalline silicon TFT (드레인 전압 바이어스에 대한 미세결정 실리콘 박막 트랜지스터의 전기적 안정성 분석)

  • Ji, Seon-Beom;Kim, Sun-Jae;Park, Hyun-Sang;Han, Min-Koo
    • Proceedings of the KIEE Conference
    • /
    • 2009.07a
    • /
    • pp.1281_1282
    • /
    • 2009
  • ICP-CVD를 이용하여 inverted staggered 구조를 갖는 미세결정 실리콘 (Nanocrystalline Silicon, nc-Si) 박막 트랜지스터(Thin Film Transistor, TFT)를 제작하였다. 또한, 소자의 특성과 전기적 안정성을 평가하였다. 실험 결과는 짧은 채널 길이를 갖는 nc-Si TFT가 긴 채널 길이의 소자보다 같은 드레인 전압 바이어스 하에서 덜 열화 됨을 알 수 있었다. 이는 드레인 전압 바이어스 하에서의 낮은 채널 캐리어 농도는 적은 defect state를 만들기 때문으로 짧은 채널 길이의 TFT가 긴 채널 길이의 TFT보다 $V_{TH}$ 열화가 적었다. 이러한 결과는 짧은 채널 길이의 nc-Si TFT가 디스플레이 분야에 있어 다양하게 응용될 것으로 기대된다.

  • PDF

Characterization of instability in a-Si:H TFT LCD utilizing copper as electrodes

  • Kuan, Yung-Chia;Liang, Shuo-Wei;Chiu, Hsian-Kun;Sun, Kuo-Sheng
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2006.08a
    • /
    • pp.747-751
    • /
    • 2006
  • The hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) with copper as source and drain electrode has been fabricated to obtain its transfer characteristics and stressed with positive and negative bias to investigate the instability variation comparing to conventional MoW-Al based TFT device. The results show that there is no copper diffusion into active layer of a-Si:H TFT, even during the thermal process. In addition, a 15-inch XGA a Si:H TFT LCD display utilizing Cu as gate electrodes has been developed.

  • PDF

Charging and Feed-Though Characteristic Simulation of TFT-LCD by Applying Several Driving Method (구동 방법에 따른 TFT-LCD의 충전 및 Feed-Though 특성 시뮬레이션)

  • Park, Jae-Woo;Kim, Tae-Hyung;Noh, Won-Yoel;Choi, Jong-Sun
    • Proceedings of the KIEE Conference
    • /
    • 2000.11c
    • /
    • pp.452-454
    • /
    • 2000
  • In recent years, the Thin Film Transistor Liquid Crystal Display (TFT-LCD) is used in a variety of products as an interfacing device between human and them. Since TFT-LCDs have trend toward larger Panel sizes and higher spatial and/or gray-scale resolution, pixel charging characteristic is very important for the large panel size and high resolution TFT-LCD pixel characteristics. In this paper, both data line precharging method and line time extension (LiTEX) method is applied to Pixel Design Array Simulation Tool (PDAST) and the pixel charging characteristics of TFT-LCD array were simulated, which were compared with the results calculated by both PDAST In which the conventional device model of a-Si TFTs and gate step method is implemented.

  • PDF

Stability Enhancement of IZOthin Film Transistor Using SU-8 Passivation Layer (SU-8 패시베이션을 이용한 솔루션 IZO-TFT의안정성 향상에 대한 연구)

  • Kim, Sang-Jo;Yi, Moonsuk
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.52 no.7
    • /
    • pp.33-39
    • /
    • 2015
  • In this work, SU-8 passivated IZO thin-film transistors(TFTs) made by solution-processes was investigated for enhancing stability of indium zinc oxide(IZO) TFT. A very viscous negative photoresist SU-8, which has high mechanical and chemical stability, was deposited by spin coating and patterned on top of TFT by photo lithography. To investigate the enhanced electrical performances by using SU-8 passivation layer, the TFT devices were analyzed by X-ray phtoelectron spectroscopy(XPS) and Fourier transform infrared spectroscopy(FTIR). The TFTs with SU-8 passivation layer show good electrical characterestics, such as ${\mu}_{FE}=6.43cm^2/V{\cdot}s$, $V_{th}=7.1V$, $I_{on/off}=10^6$, SS=0.88V/dec, and especially 3.6V of ${\Delta}V_{th}$ under positive bias stress (PBS) for 3600s. On the other hand, without SU-8 passivation, ${\Delta}V_{th}$ was 7.7V. XPS and FTIR analyses results showed that SU-8 passivation layer prevents the oxygen desorption/adsorption processes significantly, and this feature makes the effectiveness of SU-8 passivation layer for PBS.

Poly-Si Thin Film Transistor with poly-Si/a-Si Double Active Layer Fabricated by Employing Native Oxide and Excimer Laser Annealing (자연 산화막과 엑시머 레이저를 이용한 Poly-Si/a-Si 이중 박막 다결정 실리콘 박막 트랜지스터)

  • Park, Gi-Chan;Park, Jin-U;Jeong, Sang-Hun;Han, Min-Gu
    • The Transactions of the Korean Institute of Electrical Engineers C
    • /
    • v.49 no.1
    • /
    • pp.24-29
    • /
    • 2000
  • We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

  • PDF

The design and FPGA implementation of a general-purpose LDI controller for the portable small-medium sized TFT-LCD (중소형 TFT-LCD용 범용 LDI 제어기의 설계 및 FPGA 구현)

  • Lee, Si-Hyun
    • Journal of the Korea Society of Computer and Information
    • /
    • v.12 no.4
    • /
    • pp.249-256
    • /
    • 2007
  • AIn this paper, a new desist of LDI controller IC for general purpose is proposed for driving the LDI(LCD Driver Interface) controller in $4{\sim}9$ inches sized portable small-medium TFT-LCD(Thin Film Transistor addressed -Liquid Crystal Display) panel module. The designed LDI controller was verified on the FPGA(Reld Programmable Gate Array) test board, and was made the interactive operation with the commercial TFT-LCD panel successfully. The purpose of design is that it is standardized the LDI controller's operation by one LDI controller for driving all TFT-LCD panel without classifying the panel vendor, and size. The main advantage for new general-purpose LDI controller is the usage for the desist of all panel's SoG(System on a Glass) module because of the design for the standard operation. And in the previous method, it used each LDI controller for every LCD vendor, and panel size, but because a new one can drive all portable small-medium sized panel, it results in reduction of LDI controller supply price, and manufacturing cost of AV(Audio Video) board and panel. In the near future, the development of SoG IC(Integrated Circuit) for manufacturing more excellent functional TFT-LCD panel module is necessary. As a result of this research, the TFT-LCD panel can make more small size, and light weight, and it results in an upturn of domestic company's share in the world market. With the suggested theory in this paper, it expects to be made use of a basic data for developing and manufacturing for the SoG chip of TFT-LCD panel module.

  • PDF

Simulations of Gate Driving Schemes for Large Size, High Quality TFT-LCD (대면적 고화질 TFT-LCD용 게이트 Driving에 관한 Simulation)

  • Jung, Soon-Shin;Yun, Young-Jun;Kim, Tae-Hyung;Choi, Jong-Sun
    • Proceedings of the KIEE Conference
    • /
    • 1999.07d
    • /
    • pp.1809-1811
    • /
    • 1999
  • In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate delay, feed-through voltage and image sticking. Gate delay is one of the biggest limiting factors for large-screen-size, high-resolution thin-film transistor liquid crystal display (TFT/LCD) design. Many driving method proposed for TFT/LCD progress. Thus we developed gate driving signal generator. Since Pixel-Design Array Simulation Tool (PDAST) can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the driving signals of gate lines on the pixel operations can be effectively analyzed.

  • PDF

Automatic TFT-LCD Mura Inspection Based on Studentized Residuals in Regression Analysis

  • Chuang, Yu-Chiang;Fan, Shu-Kai S.
    • Industrial Engineering and Management Systems
    • /
    • v.8 no.3
    • /
    • pp.148-154
    • /
    • 2009
  • In recent days, large-sized flat-panel display (FPD) has been increasingly applied to computer monitors and TVs. Mura defects, appearing as low contrast or non-uniform brightness region, sometimes occur in manufacturing of the Thin-Film Transistor Liquid-Crystal Displays (TFT-LCD). Implementation of automatic Mura inspection methods is necessary for TFT-LCD production. Various existing Mura detection methods based on regression diagnostics, surface fitting and data transformation have been presented with good performance. This paper proposes an efficient Mura detection method that is based on a regression diagnostics using studentized residuals for automatic Mura inspection of FPD. The input image is estimated by a linear model and then the studentized residuals are calculated for filtering Mura regions. After image dilation, the proposed threshold is determined for detecting the non-uniform brightness region in TFT-LCD by means of monitoring the every pixel in the image. The experimental results obtained from several test images are used to illustrate the effectiveness and efficiency of the proposed method for Mura detection.

Temperature dependent hysteresis characteristics of a-Si:H TFT (비정질 실리콘 박막 트랜지스터 히스테리시스 특성의 온도의존성)

  • 이우선;오금곤;장의구
    • Electrical & Electronic Materials
    • /
    • v.9 no.3
    • /
    • pp.277-283
    • /
    • 1996
  • The temperature dependent characteristics of hydrogenerated amorphous silcon thin film transistor (a-Si:H TFT) with a bottom gate of N-Type <100> Si wafer were investigated. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the gate voltage increased and decreased with the small gate voltage. According to the variation of gate voltages, drain current of TFT increased by temperature increase, and hysteresis characteristics mainly depended on the temperature increase. The hysteresis current showed negative characteristics curve over 383K. The hysteresis occurance area and the differences of forward and reverse sweep were increased at the higher temperature. Hysteresis current of I$_{d}$(on/off) ratio decreased at the lower temperature and increased at the higher temperature.e.

  • PDF