• Transactions on Electrical and Electronic Materials
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• v.11 no.6
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• pp.253-256
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• 2010

Different active layer thicknesses for zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were fabricated with a poly-4-vinyphenol polymeric dielectric using injector type atomic layer deposition. The properties of the ZnO TFTs were influenced by the active thickness and width-to-length (W/L) ratio of the device. The threshold voltage of ZnO TFTs shifted positively as the active layer thickness decreased, while the subthreshold slope decreased. The W/L ratio of ZnO TFTs also affected the mobility and subthreshold slope. An optimized TFT structure exhibited an on-tooff current ratio of above 106 with solid saturation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.351-354
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• 2013

Thin-film transistors(TFTs) with silicon-zinc-tin-oxide(SiZnSnO, SZTO) channel layer are fabricated by rf sputtering method. Electrical properties were changed by different annealing treatment of dry annealing and wet annealing. This procedure improves electrical property especially, stability of oxide TFT. Improved electrical properties are ascribed to desorption of the negatively charged oxygen species from the surfaces by annealing treatment. The threshold voltage ($V_{th}$) shifted toward positive as increasing Si contents in SZTO system. Because the Si has a lower standard electrode potential (SEP) than that that of Sn, Zn, resulting in the degeneration of the oxygen vacancy ($V_O$). As a result, the Si acts as carrier suppressor and oxygen binder in the SZTO as well as a $V_{th}$ controller, resulting in the enhancement of stability of TFTs.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.507-510
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• 1998

Performance of AMLCD pixels depends on the electrical characteristics of thin film transistor switches. The high quality of LCD can be obtained by minimizing the process and device variations of TFT. The effect of process and device factors on poly-Si TFT characteristics are calculated by ATHENA and ATLAS, and the optimized design windows based on statistical design of experiment are suggested for high performance 20 inch LCD are suggested for high performance 20 inch LCD monitors.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.685-688
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• 2008

Mini-LVDS has been widely used for high speed data transmission because it provides low EMI and high bandwidth for display driver. In this paper, a Mini-LVDS output buffer with LTPS TFT process is presented which provides sufficient performance in the presence of large variation in the threshold voltage and mobility and kink effect.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.20-23
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• 2008

We proposed a-Si:H TFT (hydrogenated amorphous silicon thin film transistor) level shifter which reduced number of power sources. To reduce the number of power sources from four to two, modified bootstrapped inverter was used for the level shifter. The shift register was verified by PSPICE circuit simulation and fabricated. The fabricated level shifter successfully shifted low input (0 to 5 V) to high level output (-7 to 23 V).

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.97.4-97
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• 2001

Recently, TFT LCD (thin film transistor liquid crystal display) manufacturing industry is more concerned with the ways of cleaning large TFT LCD´s with high pixed density than ever Ultrasonic cleaners with high frequencies like 1MHz (megasonic cleaners) are effective in removing very small particles without causing mechanical damage to the surface. In this study a megasonic cleaner for TFT LCD manufacturing process is developed and the performance is evaluated through experiments. The experimental results show that the developed magasonic cleaners is effective in removing very small particle from the LCD panel.

• Electrical & Electronic Materials
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• v.17 no.7
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• pp.21-29
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• 2004

절연성 기판 위에 단결정이 아닌 반도체 박막을 이용하여 만든 전계효과 (Field Effect FET) 소자로 일반적으로 정의되는 박막 트랜지스터 (Thin Film Transistor, TFT)는 1962 RCA lab.의 Weimer에 제안되어 지금까지 많은 발전을 거듭해 왔다. ［1］ TFT는 SRAM이나 ROM에도 응용되지만, 주된 사용 분야는 능동구동방식 평판 디스플레이(Active Matrix Flat Panel Display)의 화소 스위칭 소자이다. 액정 디스플레이(Liquid Crystal Display, LCD)나 유기 전계발광 디스플레이(Organic Electro-luminescence Display, OELD) 화소의 스위칭 소자로도 TFT가 널리 사용되고 있다. (중략)

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.391-391
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• 2010

The stability enhancement of Znic oxide thin film transistor deposited by PLD-DBD has been reported here using the bias temperature stress test. Znic oxide (ZnO) thin films were deposited on $SiO_2$/Si (100) by pulsed laser deposition method with and without dielectric barrier discharge (DBD) method. The DBD is the efficient method to adopt the nitrogen ions into the thin films. The TFT characteristics of ZnO TFTs with and without Nirogen (N) doping show similar results with $I_{on/off}$ of $10^5{\sim}10^6$. However. the bias temperature stress (BTS) test of N-doped ZnO TFT with DBD shows higher stability than that of ZnO TFT.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.211.2-211.2
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• 2015

In order to investigate the effect of front channel in DAL (dual active layer) TFT (thin film transistor), we successfully fabricated DAL TFT composed of ITZO and IGZO as active layer using the solution process. In this structure, ITZO and IGZO active layer were used as front and back channel, respectively. The front channel was changed from 0.05 to 0.2 M at fixed 0.3 M IGZO of back channel. When the mol concentration of front channel was increased, the threshold voltage (VTH) was increased from 2.0 to -11.9 V and off current also was increased from 10-12 to 10-11. This phenomenon is due to increasing the carrier concentration by increasing the volume of the front channel. The saturation mobility of DAL TFT with 0.05, 0.1, and 0.2 M ITZO were 0.45, 4.3, and $0.65cm2/V{\cdot}s$. Even though 0.2 M ITZO has higher carrier concentration than 0.05 and 0.1 M ITZO, the 0.1 M ITZO/0.3 M IGZO DAL TFT has the highest saturation mobility. This is due to channel defect such as pores and pin-holes. These defect sites were created during deposition process by solvent evaporation. Due to these defect sites, the 0.1 M ITZO/0.3 M IGZO DAL TFT shows the higher saturation mobility than that of DAL TFT with front channel of 0.2 M ITZO.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.1-6
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• 2011

Low-power logic gates, i.e. inverter, NAND, and NOR, are proposed employing only n-channel oxide thin film transistors (TFTs). The proposed circuits were designed to prevent the pull-up and pull-down switches from being turned on simultaneously by using asymmetric feed-through and bootstrapping, thereby exhibited same output voltage swing as the input signal and no static current. The inverter is composed of 5 TFTs and 2 capacitors. The NAND and the NOR gates consist of 10 TFTs and 4 capacitors respectively. The operations of the logic gates were confirmed successfully by SPICE simulation using oxide TFT model.