• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.288-289
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• 2011

Indium Tin Oxide (ITO) is a typical highly Transparent Conductive Oxide (TCO) currently used as a transparent electrode material. Most widely used deposition method is the sputtering process for ITO film deposition because it has a high deposition rate, allows accurate control of the film thickness and easy deposition process and high electrical/optical properties. However, to apply high quality ITO thin film in a flexible microelectronic device using a plastic substrate, conventional DC magnetron sputtering (DMS) processed ITO thin film is not suitable because it needs a high temperature thermal annealing process to obtain high optical transmittance and low resistivity, while the generally plastic substrates has low glass transition temperatures. In the room temperature sputtering process, the electrical property degradation of ITO thin film is caused by negative oxygen ions effect. This high energy negative oxygen ions(about over 100eV) can be critical physical bombardment damages against the formation of the ITO thin film, and this damage does not recover in the room temperature process that does not offer thermal annealing. Hence new ITO deposition process that can provide the high electrical/optical properties of the ITO film at room temperature is needed. To solve these limitations we develop the Magnetic Field Shielded Sputtering (MFSS) system. The MFSS is based on DMS and it has the plasma limiter, which compose the permanent magnet array (Fig.1). During the ITO thin film deposition in the MFSS process, the electrons in the plasma are trapped by the magnetic field at the plasma limiters. The plasma limiter, which has a negative potential in the MFSS process, prevents to the damage by negative oxygen ions bombardment, and increases the heat(-) up effect by the Ar ions in the bulk plasma. Fig. 2. shows the electrical properties of the MFSS ITO thin film and DMS ITO thin film at room temperature. With the increase of the sputtering pressure, the resistivity of DMS ITO increases. On the other hand, the resistivity of the MFSS ITO slightly increases and becomes lower than that of the DMS ITO at all sputtering pressures. The lowest resistivity of the DMS ITO is $1.0{\times}10-3{\Omega}{\cdot}cm$ and that of the MFSS ITO is $4.5{\times}10-4{\Omega}{\cdot}cm$. This resistivity difference is caused by the carrier mobility. The carrier mobility of the MFSS ITO is 40 $cm^2/V{\cdot}s$, which is significantly higher than that of the DMS ITO (10 $cm^2/V{\cdot}s$). The low resistivity and high carrier mobility of the MFSS ITO are due to the magnetic field shielded effect. In addition, although not shown in this paper, the roughness of the MFSS ITO thin film is lower than that of the DMS ITO thin film, and TEM, XRD and XPS analysis of the MFSS ITO show the nano-crystalline structure. As a result, the MFSS process can effectively prevent to the high energy negative oxygen ions bombardment and supply activation energies by accelerating Ar ions in the plasma; therefore, high quality ITO can be deposited at room temperature.

• 한국재료학회지
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• 제15권3호
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• pp.149-154
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• 2005

Teflon like fluorocarbon thin films have been deposited on silicon and oxide molds as an antistiction layer for the hot embossing process by an inductively coupled plasma (ICP) chemical vapor deposition (CVD) method. The process was performed at $C_4F_8$ gas flow rate of 2 sccm and 30 W of plasma power as a function of substrate temperature. The thickness of film was measured by a spectroscopic ellipsometry. These films were left in a vacuum oven of 100, 200 and $300^{\circ}C$ for a week. The change of film thickness, contact angle and adhesion and friction force was measured before and after the thermal test. No degradation of film was observed when films were treated at $100^{\circ}C$. The heat treatment of films at 200 and $300^{\circ}C$ caused the reduction of contact angles and film thickness in both silicon and oxide samples. Higher adhesion and friction forces of films were also measured on films treated at higher temperatures than $100^{\circ}C$. No differences on film properties were found when films were deposited on either silicon or oxide. A 100 nm silicon template with 1 to $500\;{\mu}m$ patterns was used for the hot embossing process on $4.5\;{\mu}m$ thick PMMA spun coated silicon wafers. The antistiction layer of 10 nm was deposited on the silicon mold. No stiction or damages were found on PMMA surfaces even after 30 times of hot embossing at $200^{\circ}C$ and 10 kN.

• Journal of Information Display
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• 제13권2호
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.343-346
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• 1998

Ultra-thin gate oxide in MOS devices are subjected to high-field stress during device operation, which degrades the oxide and exentually causes dielectric breakdown. In this paper, we investigate the electrical properties of ultra-thin nitrided oxide (NO) and reoxidized nitrided oxide(ONO) films that are considered to be promising candidates for replacing conventional silicon dioxide film in ULSI level integration. We study vriations of I-V characteristics due to F-N tunneling, and time-dependent dielectric breakdown (TDDB) of thin layer NO and ONO depending on nitridation and reoxidation condition, and compare with thermal $SiO_{2}$. From the measurement results, we find that these NO and ONO thin films are strongly depending on its condition and that optimized reoxided nitrided oxides (ONO) films show superior dielectric characteristics, and breakdown-to-change ( $Q_{bd}$ ) performance over the NO films, while maintaining a similar electric field dependence compared to NO layer.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.319-323
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• 1988

For finding the effects of As on $TiSi_2$ formation, sputter deposited Ti film on Si substrates implanted with various doses of As have been rapid thermal annealed in Ar atmosphere at temperatures of 600-900$^{\circ}C$ for 20 sec. The sheet resistance of Ti-Silicides was examined with 4-point probe, the thickness with ${\alpha}$-step, and the As dopant behavior in Si substrates with ASR. The thickness of Ti-Silicides decreased with increasing As doping, but Ti-Silicides sheet resistance increased with increasing it. However, the critical concentration effect reported by Park et al. was not observed. We observed that the thickness of native oxide increase with increasing As doping. Thus, we concluded that native oxide act as a "barrier" for the Si diffusion.

• Bulletin of the Korean Chemical Society
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• 제30권1호
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• pp.92-96
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• 2009

A new precursor [$Zr(acac)_{3}(H_{2}O)_{2}$] was synthesized by Sonochemical technique and used to deposit thin $ZrO_{2}$ film on quartz and ceramic substrate via ultrasonic aerosol assisted chemical vapour deposition (UAACVD) at 300 ${^{\circ}C}$ in oxygen environment followed by annealing of the sample for 2-3 minutes at 500 ${^{\circ}C}$ in nitrogen ambient. The molecular structure of the precursor determined by single crystal X-ray analysis revealed that the molecules are linked through intermolecular hydrogen bonds forming pseudo six and eight membered rings. DSC and TGA/FTIR techniques were used to determine thermal behavior and decomposition temperature of the precursor and nature of evolved gas products. The optical measurement of annealed $ZrO_{2}$ film with tetragonal phase shows optical energy band gap of 5.01 eV. The particle size, morphology, surface structure and composition of deposited films were investigated by XRD, SEM and EDX.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1412-1413
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• 2011

Effects of thermal annealing on electrical characteristics of thin film transistors (TFTs) using hydrogenated zinc oxide (ZnO:H) films as active channel were extensively investigated. The ZnO:H films were deposited at room temperature by RF sputtering. The device parameters of the ZnO:H-based TFTs, such as threshold voltage ($V_{th}$), subthreshold swing (S.S.), and on-off current ratio ($I_{on}/I_{off}$), were characterized in terms of the annealing temperature as well as the gas flow ratio of $H_2$/Ar.

• 한국전기전자재료학회논문지
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• 제11권7호
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• pp.535-540
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• 1998

Thin films of PLZT were prepared on indium tin oxide(ITO) coated glass substrates by sol-gel process and annealed by rapid thermal annealing(RTA) at $750^{\circ}C$ for 5 minutes. The crystal structure of PLZT thin films were investigated for a different Zr mol% content. XRD results showed that the crystallographic structure was transitted from tetragonal to rhombohedral structure as Zr mol% increased. Raman spectroscopy results showed that the bands of spectra became broader as the amount of Zr mol% increased and two crystal phase coexisted at 2/55/45 PLZT film. Raman spectroscopy was useful for crystal structure analysis of PLZT thin films.

• 전자공학회논문지D
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• 제36D권10호
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• pp.9-16
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• 1999

Flash EEPROM 셀에서 기존의 ONO 구조의 IPD를 사용하면 peripheral MOSFET의 게이트 산화막을 성장할 때에 사용되는 세정 공정을 인하여 ONO 막의 상층 산화막이 식각되어 전하 보존 특성이 크게 열화되었으나 IPD 공정에 ONON 막을 사용하면 그 세정 공정시에 상층 질화막이 상층 산호막이 식각되는 것을 방지시켜 줌으로 전하보존 특성이 크게 개선되었다. ONON IPD 막을 갖고 있는 Flash EEPROM 셀의 전화 보존 특성의 모델링을 위하여 여기서는 굽는(bake) 동안의 전하 손실로 인한 문턱전압 감소의 실험식으로 ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$을 사용하였으며, 측정 결과 ${\beta}$=184.7, m=0.224, Ea=0.31 eV의 값을 얻었다. 이러한 0.31 eV의 활성화 에너지 값은 굽기로 인한 문턱전압의 감소가 층간 질화막 내에서의 트립된 전자들의 이동에 의한 것임을 암시하고 있다. 한편, 그 모델을 사용한 전사 모사의 결과는 굽기의 thermal budget이 낮은 경우에 실험치와 잘 일치하였으나, 반면에 높은 경우에는 측정치가 전사 모사의 결과보다 훨씬 더 크게 나타났다. 이는 thermal budge가 높은 경우에는 프로그램시에 층간 질화막 내에 트립되어 누설전류의 흐름을 차단해 주었던 전자들이 빠져나감으로 인하여 터널링에 의한 누설전류가 발생하였기 때문으로 보여졌다. 이러한 누설전류의 발생을 차단하기 위해서는 ONON 막 중에서 층간 질화막의 두께는 가능한 얇게 하고 상층 산화막의 두께는 가능한 두껍게 하는 것이 요구된다.

• Macromolecular Research
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• 제14권1호
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• pp.38-44
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• 2006

Vacuum deposited copper phthalocyanine (CuPc) was placed as a thin interlayer between indium tin oxide (ITO) electrode and a hole transporting layer (HTL) in a multi-layered, organic, light-emitting diode (OLEOs). The well-stacked CuPc layer increased the stability and efficiency of the devices. Thermal annealing after CuPc deposition and magnetic field treatment during CuPc deposition were performed to obtain a stacked-CuPc layer; the former increased the stacking density of the CuPc molecules and the alignment of the CuPc film. Thermal annealing at about 100$^{circ}C$ increased the current flow through the CuPc layer by over 25$\%$. Surface roughness decreased from 4.12 to 3.65 nm and spikes were lowered at the film surface as well. However, magnetic field treatment during deposition was less effective than thermal treatment. Eventually, a higher luminescence at a given voltage was obtained when a thermally-annealed CuPc layer was placed in the present, multi-layered, ITO/CuPc/NPD/Alq3/LiF/AI devices. Thermal annealing at about 100$^{circ}C$ for 3 h produced the most efficient, multi-layered EL devices in the present study.