• Korean Journal of Crystallography
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• v.13 no.1
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• pp.36-40
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• 2002

The order-disorder phase transition of (Fe/sub 0.61/Ni/sub 0.39/)₃V alloy that is annealed at various temperatures and time conditions was sty(lied with the examination of long-range order parameter(S) by using neutron diffraction method. As a result, the structure of the sample annealed at 680℃ for 94 h was not changed; that is, it existed iii perfect disordered state and showed face-centered cubic structure. Otherwise, samples which were annealed at temperature below 640℃ showed the value of long-range order parameter with 0 < S < 1 and phase transition into simple cubic structure partly. It was found that the annealed sample at 465℃ for 144 h is the most approximated to the thermal equilibrium state from the S-T/T/sub c/ related equation of Cowley.

• Macromolecular Research
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• v.15 no.7
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• pp.656-661
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• 2007

The effects of a neutral solvent of dioctyl phthalate (DOP) on the phase behavior of symmetric polystyrene-block-poly(n-butyl methacrylate) copolymers (PS-b-PnBMA) were assessed herein. Closed-loop phase behavior with a lower disorder-to-order transition (LDOT) and an upper order-to-disorder transition (UODT) was observed for PS-b-PnBMA/DOP solution when the quantity of DOP was carefully controlled. When the molecular weight of PS-b-PnBMA became larger, the LDOT did not appreciably change at smaller quantities of DOP. With larger quantities of DOP, the reduction in the UODT is greater than the increase in the LDOT. This behavior is discussed in accordance with a molecular theory predicated on a compressible random-phase approximation.

• Proceedings of the KIPE Conference
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• 1998.11a
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• pp.78-82
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• 1998

In this paper, the authors propose a current control system of single phase PWM AC/DC converter without the source voltage sensors. The sinusoidal input current and unity effective power factor are realised based on the estimated source voltage in the controller. The estimations of source voltage are performed based on the reduced-order Luenberger observer using actual currents. The estimated source voltage is used to accomplish unity power factor. The proposed method is proved by simulations

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.5
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• pp.936-943
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• 2009

Dynamic voltage restorer(DVR) is now more preferable enhancement than other power quality enhancement in industry to reduce the impact of voltage faults, especially voltage sags to sensitive loads. The main controllers for DVR consists of PLL(phase locked loop), compensation voltage calculator and voltage compensator. PLL detects the voltage faults and phase. Compensation voltage calculator calculates the reference voltage from the source voltage and phase. With calculated compensation voltage from PLL, voltage compensator restores the source voltage. If PLL detect ideal phase, compensation voltage calculator calculates ideal compensation voltage. Therefore, PLL for DVR is very important. This paper proposes the new method of PLL in DVR. First, the power circuit of DVR system is analyzed in order to compensate the voltage sags. Based on the analysis, new PLL for improving transient response of DVR is proposed. The proposed method uses band rejection filter(BRF) at q-axis in synchronous flame. In order to calculate compensation voltage in commercial instruments, the PQR theory is used. Proposed PLL method is demonstrated through simulation using Matlab-Simulink and experiment, and by checking load voltage, confirms operation of the DVR

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.485-488
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• 1999

In this paper, a current control system for single phase PWM AC/DC converter without the source voltage sensors is proposed. The sinusoidal input current and unity effective power factor are realised based on the estimated source voltage in the controller. The estimation of source voltage is performed by the reduced-order Luenberger observer using actual currents. The estimated source voltage is used to accomplish unity power factor. The proposed method is proved by experiments.

• Journal of Power Electronics
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• v.17 no.1
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• pp.262-271
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• 2017

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2194-2200
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• 2014

This paper presents a design of novel 2-phase 6/5 switched reluctance motor (SRM) for an air-blower application. This type of motor is suitable for the applications that require high speed and only one directional rotation as air-blower. The desired air-blower is unidirectional application, and requires a wide positive torque region without torque dead-zone. In order to get a wide positive torque region without torque dead-zone during phase commutation, asymmetric inductance characteristic with non-uniform air-gap is considered. The proposed motor can be operated at any rotor position. The proposed 6/5 SRM uses short flux path technique that achieved by means of winding configuration and lamination geometry. The purpose of short flux path is to reduce the core loss and the absorption MMF in the stator. The proposed 2-phase 6/5 SRM is verified by finite element method (FEM) analysis and Matlab-Simulink. In order to verify the design, a prototype of the proposed motor was manufactured for practical system.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.3
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• pp.279-288
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• 2013

This paper proposes a improved speed control system for five-phase squirrel-cage induction motor(IM) injecting 3rd. current harmonic components with field oriented control (FOC) A five-phase IM drives present unique characteristics due to the additional degrees of freedom and also drives possess many others advantage compared with the traditional three-phase motor drive system, such as reducing a amplitude of torque pulsation at low frequency and increasing the reliability. In order to maximize the torque per ampere, the proposed motor has concentrated windings. The produced back-electromotive force is almost trapezoidal, and the motor is supplied with the combined sinusoidal plus third harmonic of currents. There is necessary to controlled 3rd harmonic current in order to high response characteristics. For presenting the superior performance of the proposed the speed control system, experimental results are presented using a 32-bit fixed point TMS320F2812 DSP with 1.5[kW] induction motor.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.389-396
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• 2016

In order to maximize the speed of Theo Jansen Mechanism in an given design space and prototyping material, the trajectory path was maximized according to several literature reviews, and the lower leg was elongated maximally in order to minimize the shift between support phase and transfer phase.