• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2383-2390
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• 1998

As network provides diverse functionalities recently, many rpotocol standards have become complex and many implementations have appeared. Such trends require us to test th econformance of implementations, called the conformance testing. Many researches have been performed on generating test sequence and on fualt masking base don T,U,D,W methods. At this jpoint, te new problem is suggeste dwhich is calle dthe completenes s criteria. The test sequences for the conformance testing have come up with this problem as well as fault masking. In this paper, we suggest the method of generating the preverified test sequence which can avoid the completeness criteria problem. The preverified test sequence is much more reliable than others by using the preverified edge. For the reliability of conformance testing, we define the immunity of the test sequence and provide the clue for the analysis of the test results using the immunity. The analysis of the results makes it possible for us to test the implementation again with more reliability. Also, the preverified test sequence is flexible so that it is combined with the fault-tolerant sequence for fault masking.

• KIISE Transactions on Computing Practices
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• v.22 no.1
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• pp.32-37
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• 2016

In model-based testing using sequence diagrams, test cases are automatically derived from the sequence diagrams. For the generation of test cases, scenarios need to be found for representing as a sequence diagram, and to extract test paths satisfying the test coverage. However, it is hard to automatically extract test paths from the sequence diagram because a sequence diagram represents loop, opt, and alt information using CombinedFragments. To resolve this problem, we propose a transformation process that transforms a sequence diagram into an activity diagram which represents scenarios as a type of control flows. In addition, we generate test cases from the activity diagram by applying a test coverage concept. Finally, we present a case study for test cases generation from a sequence diagram.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1193-1199
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• 1996

This paper introduces an algorithm which uses MUIO and the shortest paths to minimize the length of test sequence. The length of test sequence is equal to the total number of the edges in a symmetric test graph $G^{*}$. Therefore, it is important to make a $G^{*}$ with the least number of the edges. This algorithm is based on the one proposed Shen[2]. It needs the complexity to make shortest paths but reduces the thest sequence by 1.0~9.8% over the Shen's algorithm. and this technique, directly, derives a symmetric test graph from an FMS.

• Journal of Korean Society for Quality Management
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• v.46 no.2
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• pp.311-326
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• 2018

Purpose: Using international specifications, this study classified international standards and automobile manufacturers' test items based on the kind of test used and determined the test order for ISO 16750. Methods: The effects of international standards' environmental factors were examined, based on the major impacts of the product and the results of product failure. Automobile manufacturers' test items were compared with the test item in the ISO 16750. A generic algorithm was then used to determine the test sequence for ISO 16750. Results: International standards and automobile manufacturers' common test items were classified. The test sequence of ISO 16750 was determined for five cases. Conclusion: Although mechanical and environmental tests share many common features, there are differences in the details of the tests. There is a common sequence of tests, but weights are allocated tests differently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2255-2263
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• 1994

Protocol conformance testing consists of procedures to observe an output and to check a transition state of the Implementation Under Test considered as a black box by applying an input. There are several methods to check the transition state such as Unique Input/Output(UIO) sequence. Distinguishing Sequence(DS) and Characterization Set(CS). Particularly, as a test method for a state having no UIO sequence, Partial UIO sequence method can be considered. In this paper, three properties which can be found among Partial UIO sequence and a modified algorithm using these properties are suggested.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.325-332
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• 2017

In this paper, a survey of test sequence generation methods for testing the conformance of a protocol implementation to its specification is presented. The best known methods proposed in the literature are called transition tour, distinguishing sequence, characterizing sequence, and unique input/output sequence. Also, several variants of the above methods are introduced. Applications of these methods to the finite state machine model are discussed. Then, comparative analysis of the methods is made in terms of test sequence length. Finally, conclusions are given as follows. The T-method produces the shortest test sequence, but it has the worst fault coverage. The W-method tends to produce excessively long test sequences even though its fault coverage is complete. The problem with the DS-method is that a distinguishing sequence may not exist. The UIO-method is more widely applicable, but it does not provide the same fault coverage as the DS-method.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.367-370
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• 2000

It is shown that $I_{DDQ}$ testing is very useful for shipping fault-free CMOS ICs. However, test time of $I_{DDQ}$ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of $I_{DDQ}$ testing. At first, it is Shown that $I_{DDQ}$ test time Will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed. The feasibility is checked by some experiments.riments.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• Journal of Korea Multimedia Society
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• v.1 no.1
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• pp.109-119
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• 1998

This paper describes a research result on automatic generation of Abstract Test Suite from INAP protocol in formal specifications by applying many existing related algorithms such as Rural Chinese Postman Tour and UIO sequence concepts. We use the I/O FSM generated from SDL specifications and a characterizing sequence concepts. We use the I/O FSM generated from SDL specifications and a characterizing sequence, called UIO sequence, is defined for the I/O FSM. The UIO sequence is combined with the concept of Rural Chinese Postman tour to obtain an optimal test sequence. It also proposes an estimation methodology of the fault courage for the Test Suite obtained by our method and their translation into the standardized test notation TTCN.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2357-2363
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• 1997

In this paepr, we show that the length of the test sequence can be reduced using non-minimal multiple UIO instead of minimal multiple UIO. Our test sequence generation method starts from the observation that Shen's approach cannot optimize the length of the test sequence whtn the difference between the number of incoming edge and that of outgoing edge is large. Usig the property, we propse a more efficient method to generate a UIO-based test sequence in terms of the length, and compares our method with other existing methods in terms of execution time for comformancetesting and time for generation of test sequence.