• 대한전자공학회논문지
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• 제24권3호
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• pp.535-540
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• 1987

This paper proposes a circuit partitioning method and a multifunctional BILBO which can perform the multimodule test in the case of testing VLSI circuits. By using these circuit partitioning method and multifunctional BILBO, test time and cost can be reduced greatly by performing the pipeline test method. And the quantity of circuit that shold be added for testing is also reduced in half by interposing only one BILBO between each module. Also, we confirmed that the multifunctional BILBO proposed here has high error detection capability by analyzing error detection capability of this multifunctional BILBO in mathematics.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.79-80
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• 2014

Voltage source multilevel module converter attracts more and more attention recently. The core component of the voltage source multilevel module converter is the valve based on IGBT. So the test circuit for the valve is very important, reliable test method can guarantee the converter valve design meet the operation requirement. This paper analyzes the valve voltage and current stress during the operation, and according to IEC standard test requirement, object, condition, introduces a kind of test circuit. Finally, through the simulation model, to verify the test circuit can provide the proper test condition for the voltage source multilevel module converter valve.

• 전자공학회논문지C
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• 제34C권9호
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• pp.53-60
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• 1997

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권4호
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• 전자공학회논문지A
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• 제32A권12호
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 B
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• pp.793-795
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• 2002

This study shows method of measuring mechanical stresses during short circuit test, to evaluate numerical analysis of short circuit force. As test model, 400kVA transformers are used, to acquire short circuit force acceleration sensors used. Weak region of winding is found through short circuit test, and verification data of numerical calculation is obtained.

• 한국전자통신학회논문지
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• 제9권3호
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• pp.335-342
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• 2014

본 논문에서는 하이브리드 궤도회로(Hybrid Track Circuit : HTC)의 실용화를 위한 시험방법과 그 절차에 대하여 연구하였다. 침목이나 도상 등 다양하고 특수한 선로 환경과 RFID 태그와 리더기, 안테나 구조를 고려한 시험방법을 제시함으로서 하이브리드 궤도회로의 서울메트로 구간 시범설치와 고속열차 구간 적용 연구에 활용이 가능하다. 또한 하이브리드 궤도회로 개발 프로젝트의 산출물 간 인터페이스와 설치방법 및 시험절차 등 안전하고 신뢰성 높은 결과를 도출하기 위한 방법을 제시하였다.

• 설비공학논문집
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• 제14권9호
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• pp.749-755
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• 2002

In order to develop a multi-type heat pump system with two indoor units of non-uniform capacities, the optimum refrigerant circuit was developed using capillary tubes. The refrigerant circuit was composed of four main parts, a heating circuit, a cooling circuit, a by-pass circuit and a balance circuit. The system characteristics of multi-type heat pump was investigated through the rating test and the reliability test, using the multi-type psy-chrometric calorimeter. The results of the rating test showed that the capacity of the multi-type heat pump was about 93% of the design value. In particular, the capacity of cooling single mode was about 13% higher than the design value, and the capacity of heating multi mode was about 5% higher than the design value. The reliability of the multi-type heat pump was verified by various reliability tests (overload, extension tube, freeze up, under/over charging, sweat, flood back). The optimal amount of refrigerant charge and compressor capacity were determined from the present work.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.1004-1007
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• 2005

본 논문에서는 저잡음 증폭기 (Low Noise Amplifier, LNA)를 위한 프로그램 가능한 RF (고주파) BIST (Built-In Self-Test) 회로를 제안한다. 개발된 BIST 회로는 온 칩 형태로 DC 측정만을 이용하여 LNA의 RF 변수들을 측정할 수 있다. BIST 회로는 프로그램 가능한 커패시터 뱅크 (programmable capacitor banks)를 가진 test amplifier와 RF 피크 검출기로 구성되어 있다. 이러한 온 칩 회로는 각각 GSM, Bluetooth 및 IEEE802.11g의 응용을 위해 세 가지 주파수 대, 즉 1.8GHz, 2.4GHz 및 5GHz에서 사용할 수 있도록 프로그램 되어있고, LNA가 가지는 RF 사양들, 즉 입력 임피던스 및 전압이득 등을 DC 전압으로 변화시켜주는 역할을 한다.