• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.65-78
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• 2017

Single Event Transient has a critical impact on highly integrated logic circuits which are currently common in various commercial and consumer electronic devices. Reliability against the soft and intermittent faults will become a key metric to evaluate such complex system on chip designs. Our previous work analyzing soft errors was focused on parallelizing and optimizing error propagation procedures for individual transient faults on logic and sequential cells. In this paper, we present a new propagation technique where a fault binary decision diagram (BDD) continues to merge every new fault generated from the subsequent logic gate traversal. BDD-based transient fault analysis has been known to provide the most accurate results that consider both electrical and logical properties for the given design. However, it suffers from a limitation in storing and handling BDDs that can be increased in size and operations by the exponential order. On the other hand, the proposed method requires only a visit to each logic gate traversal and unnecessary BDDs can be removed or reduced. This results in an approximately 20-200 fold speed increase while the existing parallelized procedure is only 3-4 times faster than the baseline algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.587-597
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• 2005

Flash memory based embedded computing systems are becoming increasingly prevalent.These systems typically have to provide an instant start-up time. However, we observe that mounting a file system toy flash memory takes 1 to 25 seconds mainly depending on the flash capacity. Since the flash chip capacity is doubled in every year, this mounting time will soon become the most dominant reason of the delay of system start-up time Therefore, in this paper, we present instant mounting techniques for flash file systems by storing the In-memory file system metadata to flash memory when unmounting the file system and reloading the stored metadata quickly when mounting the file system. These metadata snapshot techniques are specifically developed for NOR- and NAND-type flash memories, while at the same time, overcoming their physical constraints. The proposed techniques check the validity of the stored snapshot and use the proposed fast trash recovery techniques when the snapshot is Invalid. Based on the experimental results, the proposed techniques can reduce the flash mounting time by about two orders of magnitude over the existing de facto standard flash file system, JFFS2.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• Journal of the Korea Society of Computer and Information
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• v.12 no.1 s.45
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• pp.155-160
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• 2007

Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc.. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.135-140
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• 2008

In this paper, the spiral antenna with the center frequencies of 315MHz, 433MHz, and 447MHz for RKE system of a vehicle is designed on PCB. The antenna is microstrip line-fed, and applied PIFA concept near the feeding part to easily tune center frequency and input impedance. The PIFA-type spiral antenna with the size of $30mm{\times}20mm$ is designed on printed PCB by considering the effect of circuits and components on PCB, ECU case and vehicle body. Also chip inductor inserted dual-band spiral antenna of 315MHz and 447MHz is designed. We found that the antenna designed on PCB satisfied the antenna specifications through measurement and field test.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.32 no.10
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• pp.844-849
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• 2008

We present a novel cell deformability monitoring chip based on the digitally measured cell lysis rate which is dependent on the areal strain of the cell membrane. This method offers simple cell deformability monitoring by automated high-throughput testing system. We suggest the filter design considering the areal strain imposed on the cell membrane passing through the filter array having gradually increased orifice length. In the experiment using erythrocytes, we characterized the cell deformability in terms of average fracture areal strain which was $0.24{\pm}0.014\;and\;0.21{\pm}0.002$ for normal and chemically treated erythrocytes, respectively. We also verified that the areal strain of 0.15 effectively discriminates the deformability difference of normal and chemically treated erythrocytes, which can be applied to the clinical situation. We compared the lysis rates and their difference for the samples from different donors and found that the present chips can be commonly used without any calibration process. The experimental results demonstrate the simple structure and high performance of the present cell deformability monitoring chips, applicable to simple and cost-effective cell aging process monitoring.

• Journal of Distribution Science
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• v.22 no.7
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• pp.43-51
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• 2024

Purpose: The primary purpose of this study is to examine the influence of the Technology Acceptance Model (TAM) on the use of mobile money in Indonesia. The acceptance of technology has brought changes to society where the application of technology is aimed at identifying the best solution among the various existing alternatives. There are two types of electronic money: chip-based and server-based electronic money. Server-based electronic money is found on mobile phones. The Indonesian government has encouraged the use of electronic money and launched Less Cash Society to create a secure, efficient, and smooth payment system. Research design, data, and methodology: This study collected quantitative data from users of server-based electronic money through surveys conducted based on the sample size. The data were processed using SEM LISREL 8.70. Results: the results show that each of the TAM's fundamental elements has a significant impact. Perceived ease of use and perceived usefulness are able to encourage attitude toward using and behavioral intention to use towards actual use. Conclusions: The distribution of mobile money has a positive impact on society. Hence, mobile money providers must simplify access-recommendations made to strengthen the acceptance of mobile money via Perceived Ease of Use and Perceived Usefulness.

• Journal of Internet Computing and Services
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• v.8 no.4
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• pp.51-59
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• 2007

This paper presents the development of RFID educational system based on using 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The AT89C51ED2 VLSI chip is used for the processor of the reader and the active tag. As the development environment, Keil compiler is used for the reader and the active tag of which the programing language is C. The visual C language of the visual studio on the PC activated as the server is used for development language. To verify the function of the system, PC gets the tag's identification number through the reader and send the data to with the active tag memory a certain contents as "wite" operation. Finally the data written from the active tag's memory is sent to the PC via the reader as "read" operation and compare the received data with one already sent to the tag.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of the Korea Society of Computer and Information
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• v.13 no.6
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• pp.33-39
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• 2008

Energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in an embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. Analysis results show that the proposed instruction cache reduces the energy consumption by 20% on the average, compared to the traditional instruction cache.