JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Cascaded Propagation and Reduction Techniques for Fault Binary Decision Diagram in Single-event Transient Analysis

  • Park, Jong Kang (School of Electronic and Electrical Eng., Sungkyunkwan Univ.) ;
  • Kim, Myoungha (School of Electronic and Electrical Eng., Sungkyunkwan Univ.) ;
  • Kim, Jong Tae (School of Electronic and Electrical Eng., Sungkyunkwan Univ.)
  • Received : 2016.10.07
  • Accepted : 2017.01.02
  • Published : 2017.02.28
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Abstract

Single Event Transient has a critical impact on highly integrated logic circuits which are currently common in various commercial and consumer electronic devices. Reliability against the soft and intermittent faults will become a key metric to evaluate such complex system on chip designs. Our previous work analyzing soft errors was focused on parallelizing and optimizing error propagation procedures for individual transient faults on logic and sequential cells. In this paper, we present a new propagation technique where a fault binary decision diagram (BDD) continues to merge every new fault generated from the subsequent logic gate traversal. BDD-based transient fault analysis has been known to provide the most accurate results that consider both electrical and logical properties for the given design. However, it suffers from a limitation in storing and handling BDDs that can be increased in size and operations by the exponential order. On the other hand, the proposed method requires only a visit to each logic gate traversal and unnecessary BDDs can be removed or reduced. This results in an approximately 20-200 fold speed increase while the existing parallelized procedure is only 3-4 times faster than the baseline algorithm.

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References

  1. M. Ebrahimi, A. Evans, M. B. Tahoori, D. Alexandrescu and V. Chandra, "Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 34, No. 10, pp. 1586-1599, Apr., 2015. https://doi.org/10.1109/TCAD.2015.2422845
  2. R. D. Schrimpf, M. A. Alles, F. E. Mamouni, D. M. Fleetwood, R. A. Weller and R. A. Reed, "Soft Errors in Advanced CMOS Technologies," Proc. of 11th IEEE Solid-State and Integrated Circuit Tech., pp.1-4, Oct., 2012.
  3. H. Liu and S. Datta, "Soft-Error Performance Evaluation on Emerging Low Power Devices," IEEE Trans on. Device and Materials Reliability, Vol. 14, No. 2, pp.732-741, Apr., 2014. https://doi.org/10.1109/TDMR.2014.2316505
  4. M. Ebrahimi, H. Asadi, R. Bishnoi and M. B. Tahoori, "Layout-Based Modeling and Mitigation of Multiple Event Transients," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 35, No. 3, pp. 367-379, July, 2016. https://doi.org/10.1109/TCAD.2015.2459053
  5. M. Ebrahimi, R. Seyyedi, L. Chen and M. B. Tahoori, "Event-driven Transient Error Propagation: A Scalable and Accurate Soft Error Rate Estimation Approach," Proc. of 20th ASP-DAC, pp.743-748, Jan., 2015.
  6. H-M. Huang and C. H.-P. Wen, "Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults-From Device to Circuit Level," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 35, No. 4, pp. 586-597, Aug., 2016. https://doi.org/10.1109/TCAD.2015.2474355
  7. S. Kwon, J. K. Park, J. T. Kim, "An Approximated Soft Error Analysis Technique for Gate-level Designs," IEICE Electronic Express, Vol.11, No.10, pp.1-7, May, 2014.
  8. C.-C. Austin, H.-M. Ryan and W. H.-P. Chen, "CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate," IEEE Trans. on VLSI Systems, Vol. 21, No. 10, pp.1837-1848, Oct., 2013. https://doi.org/10.1109/TVLSI.2012.2220386
  9. M. Zhang and N. R. Shanbhag, "Soft-Error-Rate-Analysis (SERA) Methodology," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 25, No. 10, pp. 2140-2155, Aug., 2006. https://doi.org/10.1109/TCAD.2005.862738
  10. R. Rajaraman, J. S. Kim, N. Vijaykarishnan, Y. Xie and M. J. Irwin, "SEAT-LA: A Soft Error Analysis Tool for Combinational Logic," Proc. of 19th Int. Conf. on VLSI Design, pp.499-502, Jan., 2006
  11. K.-C. Wu and D. Marculescu, "A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits," IEEE Trans. on VLSI Systems, Vol. 21, No. 2, pp. 367-379, Feb., 2013. https://doi.org/10.1109/TVLSI.2012.2184145
  12. B. Zhang, W. Wang, and M. Orshansky, "FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs," Proc. of 7th Int'l. Symp. on Quality Electronic Design, pp. 755-760, Mar., 2006.
  13. J. K. Park and J. T. Kim, "An Evolutionary Approach to the Soft Error Mitigation Technique for Cell-Based Design," Advances in Electrical and Computer Eng., Vol. 15, No. 1, pp.33-40, Feb., 2015. https://doi.org/10.4316/AECE.2015.01005
  14. H. Asadi, M. B. Tahoori, M. Fazeli and S. G. Miremadi, "Efficient algorithms to accurately compute derating factors of digital circuits," Microelectronics Reliability, Vol. 52, pp.1215-1226, Jun., 2012. https://doi.org/10.1016/j.microrel.2011.12.031
  15. R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. on Computers, Vol. C-35, No. 8, pp.677-691, Aug., 1986. https://doi.org/10.1109/TC.1986.1676819
  16. M. Kim, J. K. Park and J. T. Kim, "Implementation and Analysis of parallelized Binary Decision Diagram manipulation on multicore processors," 2015 Int'l Conf. on Parallel and Distributed Processing Techniques and Applications, pp.394-397, Jul., 2015.
  17. B. Bollig and I. Wegener, "Improving the Variable Ordering of OBDDs Is NP-Complete," IEEE Trans. on Computers, Vol. 45, No. 9, pp.993-1002, Sep., 1996. https://doi.org/10.1109/12.537122
  18. N. M. Zivanov and D. Marculescu, "MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits" proc. of DAC, pp.767-772, Jul., 2006.
  19. Y. Kuo, H. Peng, and C. Wen, "Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models," proc. of 11th Int'l. Symp. on Quality Electronic Design, pp.831-838, Mar., 2010.
  20. J. F. Ziegler, "Terrestrial cosmic rays," IBM J., Vol. 40, No. 1, pp.19-39, Jan., 1996. https://doi.org/10.1147/rd.401.0019
  21. T. Karnik and P. Hazucha, "Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes," IEEE Trans. on Dependable and Secure Computing, Vol. 1, No. 2, pp. 128-143. Nov., 2004. https://doi.org/10.1109/TDSC.2004.14
  22. H.-M. Huang and C. H.-P. Wen, "Fast-Yet-Accurate Statistical Soft-Error-Rate Analysis Considering Full-Spectrum Charge Collection," IEEE Design and Test, Vol. 30, No. 2, pp.77-86, Mar. 2013. https://doi.org/10.1109/MDT.2012.2194471