• ETRI Journal
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• 제27권5호
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• 전기학회논문지
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• 제58권1호
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• Nuclear Engineering and Technology
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• 제55권3호
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• pp.1015-1020
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• 2023

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1102-1104
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• 2000

Recently effective system-on-a-chip design methodology is developed, and ASIC chip design is much studied for motor control. This paper investigates the design and implementation of ASIC chip for sensorless speed control of induction motor using VHDL which is a standarded hardware description language. The sensorless control strategy is to design an adaptive state observer for flux estimation and to estimate the rotor speed from the estimated rotor flux and stator current. The presented system is implemented using a simple electronic circuit based on FPGA.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2758-2760
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• 1999

ASIC chip design for motor control has been a subject of increasing interest since effective system-on-a-chip design methodology was developed. This paper investigates the design and implementation of ASIC chip for speed control of induction motor using VHDL which is a standarded hardware description language. The presented system is implemented using a simple electronic circuit based on FPGA.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 춘계학술대회
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• pp.888-889
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• 2015

본 논문에서는 입베디드세스템에 기초를 둔 시스템온칩을 구성하는 방법을 제안하였다. 제안한 방법은 이전의 방법에 비해 좀 더 콤팩트하고 효과적이다. 이 방법은 높은 수행시뮬레이션을 요구하고 하드웨어/소프트웨어 통합설계 툴을 사용하여 구현을 위한 실행 가능한 규격화된 적절함을 요구한다. 시스템 인터페이스 처럼 이미 존재하고 있는 부품의 재사용은 지원되지만, 작업 이후는 단지 하드웨어/소프트웨어 통합설계 툴의 프로그램에 의해 수행되어진다. 실제 설계 흐름은 모든 프로세스를 통하여 요구되는 구현으로부터 모든 설계 단계 사이의 궤환을 허용하게끔 설명되어진다. 향후 좀 더 진보된 임베디드시스템에 기초를 둔 시스템온칩을 구성하는 방법이 요구된다.

• 한국정밀공학회지
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• 제15권2호
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• pp.99-106
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• 1998

In this paper, we have constructed an expert system for semiconductor chip encapsulation which combines a knowledge-based system with CAE software. The knowledge-base module includes heuristic and pre analysis knowledge for evaluation and redesign. Evaluation of the initial design and generation of redesign recommendations can be developed from the rules as applied to a given chip package. The CAE programs can be used for simulating the filling and packing stage of encapsulation process. The expert system is a new tool which enables package design or process conditions with high yields and high productivity.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1995년도 춘계학술대회 논문집
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• pp.477-480
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• 1995

Dccisions of optimal filling conditions for the chip encapsulation have been done primarily by an ad hoc use of expertise accumulated over the years because the chip encapsulation process is quite complicated. The current CAE systems do not provide mold designers with necessary knowledge of the chip encapsulation for the successful design of optimal filling except flow simulation capability. There have been no attempts to solve the optimal filling problem in the process of the chip encapsulation. In this paper, we have constructed an design system for optimal filling to avoid short shot in the chip encapsulation process which combines an optimization methodology with CAE software.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.173-176
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• 2000

Silicon semiconductor technology agree that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduce verification time. This Paper describe the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

• 대한전자공학회논문지TE
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• 제37권5호
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• pp.56-61
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• 2000

반도체 공정 기술의 발달은 기하 급수적인 집적도의 증가를 가져오고, 이는 한 칩에 시스템을 모두 집적시키는 시스템 온 칩(SoC : System on Chip) 설계가 가능해지고, 이에 따른 설계 방법의 변화를 요구하고 있다. Soc 설계는 시스템에서 설계 사양(Specification)의 정의가 중요한 요소가 되고 있다. 본 논문에서는 MPEG 오디오 복호기에서 사용되는 IMDCT를 시스템 수준의 실행 가능한 설계 사양(Executable Specification)에 의해 설계하였다.