• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.662-665
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• 2002

This paper describes a novel converter to implement high-speed binary-to-residue conversion for moduli 2$^{n}$ - 1, 2$^{n}$ , 2$^{n}$ +2$^{\alpha}$/($\alpha$$\in$｛0,1,…,n-1｝) without using look-up table. In our implementation, the high-speed converter can be achieved, because of the modulo addition time is independent of the word length of operands by using the Signed-Digit (SD) adders inside the modulo adders. For a LSI implementation of residue SD number system with ordinary binary system, the proposed binary-to-residue converter is the efficient circuit.cient circuit.

• Journal of Biomedical Engineering Research
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• v.16 no.1
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• pp.101-106
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• 1995

In this paper, the patient monitor consisting of ECG/Respiration Amplification, Front end CPU, Main CPU, Main Controller, Video Amplifier, Display Controller, Waveform Generator, Bus & Power Supply, 8097 Processor was developed. This patient monitor measures the patient's states in the hospital such as elecctro-cardiography, respiration, blood pressurae and temperature. The control and processing methods based on micro-processor employ the flexibility, extensibility over other conventional system. The followings are incorporated in this system. First, ECG/RESP measures the respiration by impedence pneumography. Second, FECPU utilizes an Intel 8031 microcontroller. Third, Controller function originate from a LSI CRT controller.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1098-1100
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• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.81-88
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• 2002

A new pattern generator of BIST based on the pattern clustering is developed. The proposed technique embeds a pre-computed deterministic test set with low hardware overhead for test-per-clock environments. The test control logic is simple and can be synthesized automatically. Experimental results for the ISCAS benchmark circuits show that the effectiveness of the new pattern generator compared to the previous methods.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.594-596
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• 1998

In this paper, a path control switch has been developed for self-healing operation in SDH-based transmission system. The proposed switch is suitable for self-healing operations in both an Unidirectional Path Switched Ring and a 2-fiber Bidirectional Line Switched Ring. The path control switch is implemented with $0.8{\mu}m$ CMOS LSI chip. The self-healing operation of the switch is effectively done by the configuration information stored in the registers of the switch. The switch has an AU-3(51.84Mb/s) TSI(Time Slot Interchange) and has 1.25Gb/s throughput. But the higher throughput can be realized by combining two identical switches or more with the parallel architecture.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.184-186
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• 2008

리니어 발전기는 리니어 엔진의 시동에 필요한 연소조건을 만들기 위하여 전동기로 동작하다가 연소가 안정화되면 발전기로 동작을 하여 PCS(Power Conditioning System)를 통해서 전력을 계통으로 보내주게 된다. 리니어 엔진의 초기 시동을 하기 위하여 발전기는 운동주파수와 운동방향, 그리고 힘의 크기를 제어해야 하며, 발전 시에는 엔진의 동작에 맞도록 전력을 제어해야 한다. 이를 효율적으로 제어하기 위하여 MSC(Machine Side Converter)에서 상전류를 독립적으로 조절할 수 있는 H-bridge로 각 상을 구성하였다. LSI(Line Side Inverter)는 DC-Link 전압을 제어하여, MSC의 동력/발전 동작에 따라서 전력을 계통에서 받아오거나 전력을 계통으로 보내는 동작을 한다. 본 연구에서는 리니어 발전기 모델링를 통해서 PCS 제어 알고리즘을 확인하고 전체 시스템과 연동을 한 실제 운전특성에 대하여 살펴보았다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.824-829
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• 1994

High-frequency and complex vibration ultrasonic wire bonding systems are propsed and their welding characteristic are studied. Ultrasonic wire bonding is used widely for joining thin connecting wire of various electronic devices including IC or LSI. Conventional bonding systems use vibration frequency of 40 or 60 kHz and linear vibration welding tips. Complex vibration welding tip which vibrates in elliptical to circular or rectangular to square in the same or different frequency is effective to join welding specimens in shorter welding time and under smaller vibration amplitude, and furthermore high-frequency systems such as 90, 120, 190 kHz are also significantly effective. High-frequency and complex vibration welding system of 90, 120 and 190 kHz are designed. Welding characteristics of these systems are found very superior than a conventional system. Welding specimens of aluminum wire of 0.1mm diameter are successfully.

• Journal of Multimedia Information System
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• v.5 no.4
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• pp.273-276
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• 2018

In video compression standards, the entropy coding is essential to the high performance compression because redundancy of data symbols is removed. Binary arithmetic coding is one of high performance entropy coding methods. However, the dependency between consecutive binary symbols prevents improving the throughput. For the throughput enhancement, a new probability model is proposed for encoding multi-symbols at one time. In the proposed method, multi-symbol encoder is implemented with only adders and shifters, and the multiplication table for interval subdivision of binary arithmetic coding is removed. Compared to the compression ratio of CABAC of H.264/AVC, the performance degradation on average is only 1.4% which is negligible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.74-80
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• 2002

VLSI intergrated circuits like SOC(system on chip) often require a multi-clock design style for functional or performance reasons. The problems of the clock domain transition due to clock skew and clock ordering within a test cycle may result in wrong results. This paper describes a new BIST(Built-in Self Test) architecture for multi-clock systems. In the new scheme, a clock skew is eliminated by a multi-capture. Therfore, it is possible to perform at-speed test for both clock inter-domain and clock intra-domain.