• Electrical & Electronic Materials
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• v.3 no.2
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• pp.123-130
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• 1990

본 논문은 페라이트의 온도특성을 측정하기 위한 다중측정시스템의 설계에 관하여 연구한 것이다. 본 시스템은 전기로의 온도를 제어하기 위한 열전대 콘트롤러, 릴레이 동작을 제어하기 위한 릴레이 콘트롤러 및 릴레이를 구동시키기 위한 스윗칭부, 그리고 GPIB를 이용한 LCR메터 제어부와 이들을 마이크로 컴퓨터와 통신하기 버스 라인으로 구성하였다. 열전대 콘트롤러와 릴레이 콘트롤러는 8255A(Intel LSI)를 주로 이용하여 설계하였으며 릴레이로는 고주파용 릴레이를 사용하여 스윗칭 트랜지스터로 구동시키는 방법을 택하였다. 그리고 LCR-메터에는 GPIB(AD50488)보드를 사용하였다. 측정시료로서는 복합첨가제방식에 의하여 제작된 Mn-Zn-Fe계 페라이트의 시편을 사용하였으며 시료의 특성측정은 자체 제작한 자동계측시스템을 이용하여 분석하였다. 측정결과 온도보상점 T$_{o}$ 와 큐리온도 T$_{c}$ 바로 아래에서 투자율의 급격한 변화를 확인할 수 있었다. 그리고 특성의 계측에 있어서 일관성이 있고 정확한 자료를 얻을 수 있었으며 따라서 본 시스템이 인터페이스와 컴퓨터 사이의 연결성이 좋은 자동다중계측시스템으로 활용 할 수 있음을 확인한다.

• Transactions on Electrical and Electronic Materials
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• v.11 no.5
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• pp.234-237
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• 2010

Nanoenergetic materials were synthesized and the thermite reaction between the CuO nanowires and the deposited nano-Al by Joule heating was studied. CuO nanowires were grown by thermal annealing on a glass substrate. To produce nanoenergetic materials, nano-Al was deposited on the top surface of CuO nanowires. The temperature of the first exothermic reaction peak occurred at approximately $600^{\circ}C$. The released heat energy calculated from the first exothermic reaction peak in differential scanning calorimetry, was approximately 1,178 J/g. The combustion of the nanoenergetic materials resulted in a bright flash of light with an adiabatic frame temperature potentially greater than $2,000^{\circ}C$. This thermite reaction might be utilized to achieve a highly reliable selective area crystallization of amorphous silicon films.

• Proceedings of the Korea Concrete Institute Conference
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• 1993.10a
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• pp.207-212
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• 1993

When constructing highly precise production plants, for example, super LSI plants or semiconductor plants, it is important to take the necessary control countermeasures into consideration to obtain the working microvibration environment, which is directly related to product precision. Working environment of a clean room means vibration-free and there are only ultra-miro vibration which human cannot sense. In order to provide an place having a vibration-free working environment with only ultra-micro vibration it is necessary to posses a great number of vibration isolation technlogies, wide-ranging and abundant survey and teat data, and a high level of knowledge enabling comprehensive judgments to be made. In this study, experimental modal analysis is used to analyze the dynamic characteristics of double floor for vibration-proofing near apparatus which generate vibration. It is concluded that the double floor system with rubber pad inserted between floor panel and pedestal is good for vibration proof.

• Journal of electromagnetic engineering and science
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• v.15 no.4
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• pp.258-265
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• 2015

A de-embedding method for multiport networks, especially for coupled odd interconnection lines, is presented in this paper. This method does not require a conversion from S-parameters to T-parameters, which is widely used in the de-embedding technique of multiport networks based on cascaded simple two-port relations, whereas here, we apply an operation to the S-matrix to generate all the uncoupled and coupled coefficients. The derivation of the method is based on the relations of incident and reflected waves between the input of the entire network and the input of the intrinsic device under test (DUT). The characteristics of the intrinsic DUT are eventually achieved and expressed as a function of the S-parameters of the whole network, which are easily obtained. The derived coefficients constitute ABCD-parameters for a convenient implementation of the method into cascaded multiport networks. A validation was performed based on a spice-like circuit simulator, and this verified the proposed method for both uncoupled and coupled cases.

• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.610-612
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• 2013

A novel balanced distributed amplifier (DA) was proposed using novel impedance transforming MEMS baluns. The impedance transforming MEMS balun is matched to $50{\Omega}$ at one input port and $25{\Omega}$ at two output ports. It is based on the electric field mode-change method, thus it is strongly independent of frequency and very compact. The novel balanced DA consists of two $25{\Omega}$-matched DAs and these are combined by $50{\Omega}$-to-$25{\Omega}$ baluns. Theoretically, it has two times wider bandwidth and power capability than the conventional DA. So as to verify the proposed concept, we designed and fabricated a conventional DA and the proposed one using 0.15-${\mu}m$ GaAs pHEMT technology.

• ETRI Journal
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• v.32 no.1
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• pp.93-101
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• 2010

A true random number generator (TRNG) is widely used to generate secure random numbers for encryption, digital signatures, authentication, and so on in crypto-systems. Since TRNG is vulnerable to environmental changes, a deterministic function is normally used to reduce bias and improve the statistical properties of the TRNG output. In this paper, we propose a linear corrector for secure TRNG. The performance of a linear corrector is bounded by the minimum distance of the corresponding linear error correcting code. However, we show that it is possible to construct a linear corrector overcoming the minimum distance limitation. The proposed linear corrector shows better performance in terms of removing bias in that it can enlarge the acceptable bias range of the raw TRNG output. Moreover, it is possible to efficiently implement this linear corrector using only XOR gates, which must have a suitable hardware size for embedded security systems.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.613-614
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• 2006

In this paper, BSIM4's IIR(Intrinsic Input Resistance) model that has a difficulty to predict $Z_{11}$ exactly is investigated by analyzing S-parameter measurement. Then a BSIM4 macro model for 70nm RF MOSFETs is proposed. That model uses external effective gate resistance which is composed of R and parallel RC. Comparison between simulation results using proposed model and IIR model is shown. The proposed model shows a better agreement between measured and simulated results up to 20GHz.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.591-592
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• 2006

Schottky diodes for Radio-frequency identification (RFID) tag integration on chip were designed and fabricated using Samsung electronics System LSI standard $0.18{\mu}m$ CMOS process. Schottky diodes were designed as interdigitated fingers array by CMOS layout design rule. 64 types of Schottky diode were designed and fabricated with the variation of finger width, length and numbers with a $0.6{\mu}m$ guard ring enclosing n-well. Titanium was used as Schottky contact metal to lower the Schottky barrier height. Barrier height of the fabricated Schottky diode was 0.57eV. DC current - voltage measurements showed that the fabricated Schottky diode had a good rectifying properties with a breakdown voltage of -9.15 V and a threshold voltage of 0.25 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1394-1397
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• 1993

A Fuzzy Microprocessor(FMP) is presented, which is suitable for real-time control applications. The features include high speed inference of maximum 114K FLIPS at 20MHz system clocks, capability of up to 128-rule construction, and handing of 8 input variables with 8-bit resolution. In order to realize these features, the fuzzifier circuit and the processing element(PE) are well optimized for LSI implementation. The chip fabricated in 1.2$\mu\textrm{m}$ CMOS technology contains 71K transistors in 82.8 $\textrm{mm}^2$ die size and is packaged in 100-pin plastic QFP.