• Title/Summary/Keyword: synchronous operation

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Soft Switching Control Method for Photovoltaic AC Module Flyback Inverter using Synchronous Rectifier (동기 정류기를 이용한 태양광 모듈용 플라이백 인버터 소프트 스위칭 제어 기법)

  • Jang, Jin-Woo;Kim, Young-Ho;Choi, Bong-Yeon;Jung, Yong-Chae;Won, Chung-Yuen
    • The Transactions of the Korean Institute of Power Electronics
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    • v.18 no.4
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    • pp.312-321
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    • 2013
  • In this paper, high efficiency control method for flyback inverter with synchronous rectifier(SR) based on photovoltaic AC modules is proposed. In this control method, the operation of SR is classified according to the voltage spike across main switch SP. When the voltage spike across SP is lower than the rating voltage of SP, the operation of active clamp circuit is interrupted for reducing the switching loss of auxiliary switch. In this time, the SR is operated for soft-switching of SP. When the voltage spike across Sp is higher than the rating voltage of SP, the operation of active circuit is activated for reducing the voltage spike. The SR is operated for reducing the conduction loss of secondary output diode. Thus, a switching loss of the main switch can be reduced in low power region, and weighted-efficiency can be improved. A theoretical analysis and the design principle of the proposed method are provided. And validity is confirmed through simulation and experimental results.

A study on the low power architecture of multi-giga bit synchronous DRAM's (Giga Bit급 저전력 synchronous DRAM 구조에 대한 연구)

  • 유회준;이정우
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.11
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    • pp.1-11
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    • 1997
  • The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

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Optimization of Sun-synchronous Spacecraft Constellation Orbits (태양동기궤도 위성군 궤도 최적화에 관한 연구)

  • Kim, Hwayeong;No, Tae Soo;Jung, Okchul;Chung, Daewon;Choi, Jin-Heng
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.43 no.2
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    • pp.141-148
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    • 2015
  • This paper presents a sun-synchronous orbit design which effectuvely includes the requirements derived from spacecraft to ground station contact and spacecraft to target image accessibility. For this purpose, operation parameters of multiple spacecraft are defined as Contact Overlap, Contact Overlap Gap, Access Overlap, Access Overlap Gap. These parameters are used to form a Figure of Merit that reflects the operational requirements. The Figure of Merit is optimized to increase the efficiency of operating multiple spacecraft in constellation and is used to determine the operational orbit of each spacecraft that constitutes the constellation.

Surgical Strategy for Primary Colorectal Carcinoma and Synchronous Pulmonary Metastasis Resection

  • Kim, Tae Yeon;Cho, Jong Ho;Choi, Yong Soo;Kim, Hong Kwan;Kim, Jhin Gook;Shim, Young Mog
    • Journal of Chest Surgery
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    • v.55 no.1
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    • pp.37-43
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    • 2022
  • Background: The surgical strategy for single-stage resection of primary colorectal cancer (CRC) and synchronous pulmonary metastases remains a matter of debate. Methods: Perioperative data of patients who underwent single-stage resection of primary CRC and synchronous pulmonary metastases were compared to those of patients who underwent 2-stage resections. The demographic data, number of metastases, type of pulmonary and colorectal resections, operation time, blood loss, postoperative complications, morbidities, mortality, medical costs, and length of hospital stay were analyzed. Results: Twenty-two patients underwent single-stage resection of primary CRC and pulmonary metastases, while 27 patients underwent 2-stage resection. Tumor size and the number of pulmonary metastases were not significantly different between the 2 groups. The extent of pulmonary metastasectomy and abdominal procedures were similar in both groups, as was the thoracic surgical approach (video-assisted thoracic surgery vs. thoracotomy). However, open laparotomy was performed more frequently in the 2-stage group than in the single-stage group (p=0.045), which also had a longer total anesthetic time (p=0.013). The operation time, medical costs, estimated blood loss, complication rates, and severity were similar in both groups, but the length of hospital stay was shorter in the single-stage group (p<0.001). Conclusion: Single-stage colorectal and pulmonary resection shortened the overall hospital stay, with no significant changes in operation time, medical costs, hospital mortality, and morbidity. Therefore, single-stage resection could be a good surgical strategy in selected patients.

Exploring Factors for the Effective Operation of Hybrid Learning Integrating Face-to-Face with Online Synchronous Environment: Focusing on the Experience of Elementary School Teachers (면대면과 실시간 온라인 환경이 통합된 하이브리드 수업의 효과적 운영을 위한 요소 탐색: 초등교사의 경험을 중심으로)

  • Han, Hyeong Jong
    • The Journal of the Convergence on Culture Technology
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    • v.8 no.6
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    • pp.79-88
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    • 2022
  • The purpose of this study was to explore which factors should be considered mainly in operating hybrid learning in which offline and synchronous online environments are integrated in elementary education. Using qualitative data through interview and so on for 8 elementary school teachers with experience in operating hybrid learning, major consideration factors were identified. Before class, it is necessary to increase the level of understanding through concrete guidance or education for what the characteristics of hybrid learning are. The redesign of the environment including hardware and software technology is considered because the foundation was not established properly so that effective operation was difficult. In particular, based on the simultaneity and interactivity between the environments, activities which learners can connect and participate in the two environments should be considered. Further, design strategies to guide the operation of teaching and learning will be developed.

Analysis of effect on power system considering the maximum penetration limit of wind power (풍력발전 한계운전용량에 대한 계통영향 분석)

  • Myung, Ho-San;Kim, Bong-Eon;Kim, Hyeong-Taek;Kim, Se-Ho
    • Journal of the Korean Solar Energy Society
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    • v.32 no.3
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    • pp.19-25
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    • 2012
  • About supply and demand to see that you need to match, the limitations of wind power capacity is low demand and the commitment of the general generator will exist between the minimum generation. if the turbine's output can be controlled, The limitation of wind power capacity will be adopted based on instant power generation. Namely, The minimum limits of wind power generation based load operation by calculating the amount that is higher than if the output should be restricted to highest operation. in this paper, we committed to the demand for low enough that the combination of the general generator of wind power capacity to accommodate the operation of determining whether the limit is intended to. For this, power system analysis program PSS/E was used, Jeju system by implementing the model simulations were performed.

Transformer-Reuse Reconfigurable Synchronous Boost Converter with 20 mV MPPT-Input, 88% Efficiency, and 37 mW Maximum Output Power

  • Im, Jong-Pil;Moon, Seung-Eon;Lyuh, Chun-Gi
    • ETRI Journal
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    • v.38 no.4
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    • pp.654-664
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    • 2016
  • This paper presents a transformer-based reconfigurable synchronous boost converter. The lowest maximum power point tracking (MPPT)-input voltage and peak efficiency of the proposed boost converter, 20 mV and 88%, respectively, were achieved using a reconfigurable synchronous structure, static power loss minimization design, and efficiency boost mode change (EBMC) method. The proposed reconfigurable synchronous structure for high efficiency enables both a transformer-based self-startup mode (TSM) and an inductor-based MPPT mode (IMM) with a power PMOS switch instead of a diode. In addition, a static power loss minimization design, which was developed to reduce the leakage current of the native switch and quiescent current of the control blocks, enables a low input operation voltage. Furthermore, the proposed EBMC method is able to change the TSM into IMM with no additional time or energy loss. A prototype chip was implemented using a $0.18-{\mu}m$ CMOS process, and operates within an input voltage range of 9 mV to 1 V, and an output voltage range of 1 V to 3.3 V, and provides a maximum output power of 37 mW.

Subsection Synchronous Current Harmonic Minimum Pulse Width Modulation for ANPC-5L Inverter

  • Feng, Jiuyi;Song, Wenxiang;Xu, Yuan;Wang, Fei
    • Journal of Electrical Engineering and Technology
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    • v.12 no.5
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    • pp.1872-1882
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    • 2017
  • Medium voltage drive systems driven by high-power multi-level inverters operating at low switching frequency can reduce the switching losses of the power device and increase the output power. Employing subsection synchronous current harmonic minimum pulse width modulation (CHMPWM) technique can maintain the total harmonic distortion of current at a very low level. It can also reduce the losses of the system, improve the system control performance and increase the efficiency of DC-link voltage accordingly. This paper proposes a subsection synchronous CHMPWM approach of active neutral point clamped five-level (ANPC-5L) inverter under low switching frequency operation. The subsection synchronous scheme is obtained by theoretical calculation based on the allowed maximum switching frequency. The genetic algorithm (GA) is adopted to get the high-precision initial values. So the expected switching angles can be achieved with the help of sequential quadratic programming (SQP) algorithm. The selection principle of multiple sets of the switching angles is also presented. Finally, the validity of the theoretical analysis and the superiority of the CHMPWM are verified through both the simulation results and experimental results.

A Design of Digital DLL Circuits For High-Speed Memory (고속 메모리동작을 위한 디지털 DLL회로 설계)

  • Lee, Joong-Ho;Cho, Sang-Bock
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.7
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    • pp.43-49
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    • 2000
  • We proposed ADD(Alternate Directional Delay) circuit technique as the DLL(Delay Locked Loop) circuits which technique is established the data valid window(tDV) in DDR(Double Data Rate) Synchronous DRAM. This technique could be decrease area-overhead which it could generated bidirectional clock simultaneously using only one delay chain block. In this paper for high speed memory with relatively small size. This technique decreased area-overhead more 2 times than SMD(Synchronous Mirror Delay) technique. ADD technique has 50ps-140ps jitter and the operation frequency has 166MHz-66MHz range.(at 2.5V, TYP. condition)

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Comparative Study of the Behavior of a Wind Farm Integrating Three Different FACTS Devices

  • Sarrias, Raul;Gonzalez, Carlos;Fernandez, Luis M.;Garcia, Carlos Andres;Jurado, Francisco
    • Journal of Electrical Engineering and Technology
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    • v.9 no.4
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    • pp.1258-1268
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    • 2014
  • Improving grid connection of wind farms is a relevant issue to be addressed, especially for fixed-speed wind turbines. Certain elements, such as FACTS (Flexible AC Transmission Systems), are able to perform voltage and reactive power regulation in order to support voltage stability of wind farms, and compensate reactive power consumption from the grid. Several devices are grouped under the name of FACTS, which embrace different technologies and operating principles. Here, three of them are evaluated and compared, namely STATCOM (Static Synchronous Compensator), SVC (Static Var Compensator) and SSSC (Static Synchronous Series Compensator). They have been modeled in MATLAB/Simulink, and simulated under various scenarios, regarding both normal operation and grid fault conditions. Their response is studied together with the case when no FACTS are implemented. Results show that SSSC improves the voltage stability of the wind farm, whereas STATCOM and SVC provide additional reactive power.