• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.2A
• /
• pp.176-186
• /
• 2006

In this paper, we propose an enhanced symbol detector algorithm for 2.45GHz LR-WPAN(Low-Rate Wireless Personal Area Network) receiver. Because the frequency offset of $\pm$80ppm on 2.45GHz band is recommended in IEEE 802.15.4 LR-WPAN(Low-Rate Wireless Personal Area Network) specification, a symbol detector algorithm having stable operation in the channel environment with large frequency offset is required. For robustness to the frequency offset, non-coherent detection-based symbol detector algorithm is typically applied in the LR-WPAN receiver modem. However, the noncoherent symbol detector has increased performance degradation and hardware complexity due to squaring loss of I/Q squaring operation. Therefore we propose a coherent detection-based symbol detector algorithm with frequency offset compensation using a preamble symbol. The proposed algorithm is more suitable for LR-WPAN receiver aimed at low-cost, low-power and low-complexity than the non-coherent symbol detector, since it can reduce performance degradation due to squaring loss of I/Q squaring operation and implementation complexity. Simulation results show that the proposed algorithm has performance improvement of about 1dB in various channel environments.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.447-448
• /
• 2008

This paper presents a low-complexity design and implementation results of a multi-input multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) symbol detector for high speed wireless LAN (WLAN) systems. The proposed spatial division multiplexing (SDM) symbol detector is designed by HDL and synthesized to gate-level circuits using 0.18um CMOS library. The total gate count for the symbol detector is 238K.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.255-266
• /
• 2015

In this paper, a low-complexity and low-power soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multi-stage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clock-gating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately $0.31mm^2$ with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

• Journal of Communications and Networks
• /
• v.8 no.2
• /
• pp.205-211
• /
• 2006

This paper considers the maximum likelihood (ML) detection of 16-ary differential amplitude and phase shift keying (DAPSK) in Rayleigh fading channels. Based on the conditional likelihood function, two new receiver structures, namely ML symbol-by-symbol receiver and ML sequence receiver, are proposed. For the symbol-by-symbol detection, the conventional DAPSK detector is shown to be sub-optimum due to the complete separation in the phase and amplitude detection, but it results in very close performance to the ML detector provided that its circular amplitude decision thresholds are optimized. For the sequence detection, a simple Viterbi algorithm with only two states are adopted to provide an SNR gain around 1 dB on the amplitude bit detection compared with the conventional detector.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.3
• /
• pp.41-50
• /
• 2010

In this paper, an area-efficient symbol detector is proposed for MIMO communication systems with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate，the complexity of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of logic slices for the proposed symbol detection is 52490 and the number of DSP48s (dedicated multiplier) is 52, which are reduced by 35.3% and 85.3%, respectively, compared with the conventional architecture.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.6
• /
• pp.34-42
• /
• 2014

This paper presents a low-complexity and high-throughput symbol detector for two-spatial-stream multiple-input multiple-output systems based on the modified maximum-likelihood symbol detection algorithm. In the proposed symbol detector, the cost function is calculated incrementally employing a multi-cycle architecture so as to eliminate the complex multiplications for each symbol, and the slicing operations are performed hierarchically according to the range of constellation points by a pipelined architecture. The proposed architecture exhibits low hardware complexity while supporting complicated modulations such as 256 QAM. In addition, various modulations and antenna configurations are supported flexibly by reconfiguring the pipeline for the slicing operation. The proposed symbol detector is implemented with 38.7K logic gates in a $0.11-{\mu}m$ CMOS process and its throughput is 166 Mbps for $2{\times}$3 16-QAM and 80Mbps for $2{\times}3$ 64-QAM where the operating frequency is 478 MHz.

• Journal of Advanced Navigation Technology
• /
• v.14 no.2
• /
• pp.220-226
• /
• 2010

In this paper, an low power symbol detector is proposed for MIMO communication system with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing (SM) mode and spatial diversity (SD) mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block and using the dedicated clock MIMO modes, the power of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and synthesized to logic gates using a $0.13-{\mu}m$ CMOS standard cell library. The power consumption was estimated by using Synopsys Power CompilerTM, which is reduced by maximum 85%, compared with the conventional architecture.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.86-89
• /
• 1999

In this paper, we propose a new architecture of the fast symbol timing synchronization system which has some shared hardware blocks in order to reduce the hardware complexity. The proposed system consists of received power detector, correlation power detector using shared complex moving adders, and 2-step peak detector. Our system has detected FFT starting point within three Symbols using first two reference symbols of the frame in wireless ATM system. The new architecture was designed and simulated using VHDL. Our proposed architecture also detects a correct symbol timing synchronization within three symbols under a multi-path fading channel.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.7
• /
• pp.545-551
• /
• 2013

Timing recovery loop composed of the Timing Error Detector(TED), loop filter and resampler is widely used for the timing synchronization in MQASK receivers. Since TED is sensitive to the delay between the symbol period of the signal and sampling period, the output is averaged out when the symbol rate and sampling rate are quite different the recovery loop cannot work at all. This paper presents a sampling frequency discriminator (SRD), which detects the frequency offset of the sampling clock to the symbol clock of the MQASK data transmitted. Employing the SRD, the closed loop timing recovery scheme performs the frequency-aided timing acquisition and achieve the synchronization at extremely high sampling frequency offset, which can be used in variable symbol rate MQASK receivers.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.77-80
• /
• 1999

This paper deals with a design of a symbol timing recovery circuit of QAM using the interpolation in AWGN channel. To reduce timing jitter and the amount of processing data, we employ MGA (Modified Gardner Algorithm) as a symbol timing error detector which is called NDA(Nondecision Directed Algorithm). We show the characteristics (S-curve and the variance) of timing error detector with the roll-off factor of a shaping filter, which are compared with GA. Also, we compare the BER curve of interpolation method with that of ideal case. The performance of the STR is shown to be close to that of ideal case. This result shows that this method can be useful to implement symbol timing recovery circuit for multi-level modulation.