• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.550-556
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• 2016

Polar codes are one of the most favorable capacity-achieving codes due to their simple structure and low decoding complexity. However, because of the disappointing decoding performance realized using conventional successive cancellation (SC) decoders, polar codes cannot be used directly in practical applications. In contrast to conventional SC decoders, list SC (SCL) decoders with large list sizes (e.g. 32) achieve performances very close to those of maximum-likelihood (ML) decoders. In SCL decoders with large list sizes, however, hardware increase is a severe problem because an SCL decoder with list size L consists of L copies of an SC decoder. In this paper, we present a low-area SCL decoder architecture that applies the proposed merged processing element-sharing (MPES) algorithm. A merged processing element (MPE) is the basic processing unit in SC decoders, and the required number of MPEs is L(N-1) in conventional SCL decoders. Using the proposed algorithm reduces the number of MPEs by about 70% compared with conventional SCL decoders when the list size is larger than 32.

• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.725-732
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• 2002

Block-wise MAP (Maximum A posteriori) decoding algorithm for turbo-codes requires less memory than Log-MAP decoding algorithm. The ER (Bit Error Rate) performance of previous block-wise MAP decoding algorithm depend on the block length and training length. To maximize hardware utilization and perform successive decoding, the block length is set to be equal to the training length in previous MAP decoding algorithms. Simulation result on the BER performance shows that the EBR performance can be maintained with shorter blocks when training length is sufficient. This paper proposes an architecture for area efficient block-wise MAP decoder. The proposed architecture employs the decoding schema for reducing memory by using the training length, which in N times larger than block length. To efficiently handle the proposed schema, a pipelined architecture is proposed. Simulation results show that memory usage can be reduced by 30%~45% in the proposed architecture without degrading the BER performance.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.3156-3167
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• 2020

One drawback of polar codes is that they are not universal, that is, to achieve optimal performance, different polar codes are required for different kinds of channel. This paper proposes a polar code construction scheme for Nakagami-m fading channel. The scheme fully considers the characteristics of Nakagami-m fading channel, and uses the optimized Bhattacharyya parameter bounds. The constructed code is applied to an orthogonal frequency division multiplexing (OFDM) system over Nakagami-m fading channel to prove the performance of polar code. Simulation result shows the proposed codes can get excellent bit error rate (BER) performance with successive cancellation list (SCL) decoding. For example, the designed polar code with cyclic redundancy check (CRC) aided SCL (L = 8) decoding achieves 1.1dB of gain over LDPC at average BER about 10^-5 under 4-quadrature amplitude modulation (4QAM) while the code length is 1024, rate is 0.5.

• Journal of Communications and Networks
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• v.17 no.6
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• pp.609-621
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• 2015

Recently, a variety of reduced complexity soft-in soft-output detection algorithms have been introduced for iterative detection and decoding (IDD) systems. However, it is still challenging to implement soft-in soft-output detectors for MIMO systems due to heavy burden in computational complexity. In this paper, we propose a soft detection algorithm for MIMO systems which performs close to the full dimensional joint detection, yet offers significant complexity reduction over the existing detectors. The proposed algorithm, referred to as soft-input soft-output successive group (SSG) detector, detects a subset of symbols (called a symbol group) successively using a deliberately designed preprocessing to suppress the inter-group interference. In fact, the proposed preprocessor mitigates the effect of the interfering symbol groups successively using a priori information of the undetected groups and a posteriori information of the detected groups. Simulation results on realistic MIMO systems demonstrate that the proposed SSG detector achieves considerable complexity reduction over the conventional approaches with negligible performance loss.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2197-2204
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• 2009

In this paper, we analyze the performance of the sphere decoding algorithm at MIMO system. The BER performance of this algorithm is the same as that of ML receiver, but computational complexity of SD algorithm is much less than that of ML receiver. The independent signals from each transmit antennas are modulated by using the QPSK and 16QAM modulation in the richly scattered Rayleigh flat-fading channel. The received signals from each receivers is independently detected by the receiver using Fincke & Pohst SD algorithm, and the BER output of the algorithm is compared with those of ZF, MMSE, SIC, and ML receivers. We also investigate the Viterbo & Boutros SD algorithm which is the modified SD algorithm, and the BER performance and the floting point operations of the algorithms are comparatively studied.

• International journal of advanced smart convergence
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• v.10 no.2
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• pp.1-9
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• 2021

In the Internet-of-Things (IoT) and artificial intelligence (AI), complete implementations are dependent largely on the speed of the fifth generation (5G) networks. However, successive interference cancellation (SIC) in non-orthogonal multiple access (NOMA) of the 5G mobile networks can be still decoding latency and receiver complexity in the conventional SIC NOMA scheme. Thus, in order to reduce latency and complexity of inherent SIC in conventional SIC NOMA schemes, we propose a rate-lossless non-SIC NOMA scheme. First, we derive the closed-form expression for the achievable data rate of the asymmetric 2PAM non-SIC NOMA, i.e., without SIC. Second, the exact achievable power allocation interval of this rate-lossless non-SIC NOMA scheme is also derived. Then it is shown that over the derived achievable power allocation interval of user-fairness, rate-lossless non-SIC NOMA can be implemented. As a result, the asymmetric 2PAM could be a promising modulation scheme for rate-lossless non-SIC NOMA of 5G networks, under user-fairness.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.51-53
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• 2015

In this paper, we propose a new relay selection technique which utilizes interference cancellation with decoding information at multiple relays for buffer-aided successive relaying systems. The transmitting relay is selected if its own transmission to the destination is successful and the number of relays which can successfully decode the data from the source is the maximum at the same time. Simulation results show that the proposed relay selection technique significantly outperforms the conventional relay selection scheme in terms of outage probability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.560-569
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• 2005

This paper proposes an algorithm for transmit antenna selection in a multi-input multi-output(MIMO) spatial multiplexing system with per antenna rate control(PARC) and an ordered successive interference cancellation (OSIC) receiver. The active antenna subset is determined at the receiver and conveyed to the transmitter using feedback information on transmission rate per antenna. We propose a serial decision procedure consisting of a successive process that tests whether antenna selection gain exists when the antenna with the lowest pre-processing signal to interference and noise ratio(SINR) is discarded at each stage. Furthermore, we show that 'reverse detection ordering', whereby the signal with the lowest SINR is decoded at each stage of successive decoding, widens the disparities among fractions of the whole capacity allocated to each individual antenna and thus maximizes a gain of antenna selection. Numerical results show that the proposed reverse detection ordering based serial antenna selection approaches the closed-loop MIMO capacity and that it induces a negligible capacity loss compared with the heuristic selection strategy even with considerably reduced complexity.