• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.263-268
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• 2003

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.211-213
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• 2008

The TFTs from ZnO semiconductor with hafnium oxide dielectrics were prepared by atomic layer deposition to characterize the electrical properties. Good electrical properties of oxide TFT was obtained with channel mobility of $2.1\;cm^2/Vs$, threshold voltage of 0 V, the subthreshold slope of 0.9 V/dec, and on to off current ratio of $10^6$.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.718-722
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• 2006

The dependence of n-channel 2 shot SLS poly-Si TFT characteristics on the DOS (density of states) parameters was investigated by using a device simulation. Device performances were most sensitive to the DOS of poly-Si/gate insulator (GI) interface and poly-Si active layer. Deep level states at the poly-Si/GI interfaces strongly affect the subthreshold slope.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.543-545
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• 2009

With injection-type source delivery system of atomic layer deposition (ALD), bottom-contact and bottom-gate thin-film transistors (TFTs) were fabricated with a poly-4-vinyphenol polymeric dielectric for the first time. The properties of the ZnO TFT were greatly influenced by the device structure and the process conditions. The zinc oxide TFTs exhibited a channel mobility of 0.43 $cm^2$/Vs, a threshold voltage of 0.85 V, a subthreshold slope of 3.30 V/dec, and an on-to-off current ratio of above $10^6$ with solid saturation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.485-488
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• 1999

In this paper, the effects of back-gate bias on n-channel SOI MOSFETs has been systematically investigated. Back-gate surface is accumulated when negative bias is applied. It is found that the driving current ability of SOI MOSFETs is reduced because the threshold voltage and subthreshold slope are increased and transconductance is decreased due to the hole accumulation in Si body.

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.43-44
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• 1993

In this study SOI MOSFET model of the structure with 4-terminals and 3-interfaces is proposed. An SOI MOSFET is modeled with the equivalent circuit considered the interface capacitances. Parameters of SOI MOSFET device are extracted, and the electrical characteristics due to back-bias change is simulated. In SOI-MOSFET model device we describe the characteristics of threshold voltage, subthreshold slope, maxium electrical field and drain currents in the front channel when the back channel condition move into accmulation, depletion, and inversion regions respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.61-64
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• 1994

The NMOSFET with gate length of 0.1$\mu$m is fabricated by mix-and-match method. In this device, the electron beam lithography is used to form the gate layer, while other layers are formed by the stepper. The gate oxide is 7nm thick, and the device structure is normal LDD structure. The saturation Gm for gate length of 0.1$\mu$m is 246mS/mm. The subthreshold slope is 180mV/decade for 0.1$\mu$m gate length, but the slope is 80mV/decade for 0.3$\mu$m gate length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.135-141
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• 2014

In this paper, the device design guideline to reduce the threshold voltage variation with fin width in junctionless MuGFET has been suggested. It has been observed that the threshold voltage variation was increased with increase of fin width in junctionless MuGFETs. To reduce the threshold voltage variation with fin width in junctionless MuGFETs, 3-dimensional device simulation with different gate dielectric materials, silicon film thickness, and an optimized fin number has been performed. The simulation results showed that the threshold voltage variation can be reduced by the gate dielectric materials with a high dielectric constant such as $La_2O_3$ and the silicon film with ultra-thin thickness even though the fin width is increased. Particularly, the reduction of the threshold voltage variation and the subthreshold slope by reducing the fin width and increasing the fin numbers is known the optimized device design guideline in junctionless MuGFETs.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.6-12
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• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.33-37
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• 2014

We have developed a novel passivation process employing a sacrificial gallium oxide process in order to recover the surface damage in AlGaN/GaN HFETs. Even with a conventional prepassivation process, surface damage during high temperature ohmic annealing cannot be avoided completely. Therefore, it is necessary to recover the damaged surface to avoid the characteristic degradation. In this work, a sacrificial gallium oxide process has been proposed in which the damaged surface after ohmic annealing was oxidized by oxygen plasma treatment and thereafter etched back using HCl. As a result, the leakage current was dramatically reduced and thus the subthreshold slope was significantly improved. In addition, the maximum drain current level was increased from 594 to 634 mA/mm. To verify the effects, the surface conditions were carefully investigated using X-ray photoelectron spectroscopy.