• Journal of the Korean Applied Science and Technology
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• v.24 no.1
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• pp.54-60
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• 2007

이 논문에서는 게이트 절연막 위에 vapor deposition polymerization(VDP)방법을 사용하여 성막한 유기 점착층을 진공 열증착하여 유기 박막 트랜지스터(OTFTs)소자를 제작할 수 있음을 증명하였다. 우리가 제작한 Staggered-inverted top-contact 구조를 사용한 유기 박막 트랜지스터는 전기적 output 특성이 포화 영역안에서는 포화곡선을, triode 영역에서는 비선형적인 subthreshold를 확실히 볼 수 있음을 발견했다. $0.2{\mu}m$ 두께를 가진 게이트 절연막위에 유기 점착층을 사용한 OTFTs의 장 효과 정공의 이동도와 문턱전압, 그리고 절멸비는 각각, 약 0.4cm2/Vs, -0.8V, 106 이 측정되었다. 게이트 절연막의 점착층으로써 폴리이미드의 성막을 위해, 스핀코팅 방법 대신 VDP 방법을 도입하였다. 폴리이미드 고분자막은 2,2bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride(6FDA)와 4,4'-oxydianiline(ODA)을 고진공에서 동시에 열 증착 시킨 후, 그리고 $150^{\circ}C$에서 1시간, 다시 $200^{\circ}C$에서 1시간 열처리하여 고분자화된 막을 형성하였다. 그리고 점착층이 OTFTs의 전기적 특성에 주는 영향을 설명하기 위해 비교 연구하였다.

• ETRI Journal
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• v.37 no.6
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• pp.1135-1142
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• 2015

Multilayered ZnO-$SnO_2$ heterostructure thin films consisting of ZnO and $SnO_2$ layers are produced by alternating the pulsed laser ablation of ZnO and $SnO_2$ targets, and their structural and field-effect electronic transport properties are investigated as a function of the thickness of the ZnO and $SnO_2$ layers. The performance parameters of amorphous multilayered ZnO-$SnO_2$ heterostructure thin-film transistors (TFTs) are highly dependent on the thickness of the ZnO and $SnO_2$ layers. A highest electron mobility of $43cm^2/V{\cdot}s$, a low subthreshold swing of a 0.22 V/dec, a threshold voltage of 1 V, and a high drain current on-to-off ratio of $10^{10}$ are obtained for the amorphous multilayered ZnO(1.5nm)-$SnO_2$(1.5 nm) heterostructure TFTs, which is adequate for the operation of next-generation microelectronic devices. These results are presumed to be due to the unique electronic structure of amorphous multilayered ZnO-$SnO_2$ heterostructure film consisting of ZnO, $SnO_2$, and ZnO-$SnO_2$ interface layers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1422-1428
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• 2014

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.330-332
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• 2009

Highly stable bottom gate thin film transistors(TFTs) with a zinc indium tin oxide(Zn-In-Sn-O:ZITO) channel layer have been fabricated by rf-magnetron co-sputtering using a indium tin oxide(ITO:90/10), a tin oxide and a zinc oxide targets. The ZITO TFT (W/L=$40{\mu}m/20{\mu}m$) has a mobility of 24.6 $cm^2$/V.s, a subthreshold swing of 0.12V/dec., a turn-on voltage of -0.4V and an on/off ratio of >$10^9$. When gate field of $1.8{\times}10^5$ V/cm was applied with source-drain current of $3{\mu}A$ at $60^{\circ}C$, the threshold voltage shift was ~0.18 V after 135 hours. We fabricated AM-OLED driven by highly stable bottom gate Zn-In-Sn-O TFT array.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.6
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• pp.229-235
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• 2002

This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.8
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• pp.469-473
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• 2017

We investigated the effect of different thin-film thicknesses (25, 30, and 40 nm) on the electrical performance of solution-processed indium-zinc-oxide (IZO) thin-film transistors (TFTs). The structural properties of the IZO thin films were investigated by atomic force microscopy (AFM). AFM images revealed that the IZO thin films with thicknesses of 25 and 40 nm exhibit an uneven distribution of grains, which deforms the thin film and degrades the performance of the IZO TFT. Further, the IZO thin film with a thickness of 30 nm exhibits a homogeneous and smooth surface with a low RMS roughness of 1.88 nm. The IZO TFTs with the 30-nm-thick IZO film exhibit excellent results, with a field-effect mobility of $3.0({\pm}0.2)cm^2/Vs$, high Ion/Ioff ratio of $1.1{\times}10^7$, threshold voltage of $0.4({\pm}0.1)V$, and subthreshold swing of $0.7({\pm}0.01)V/dec$. The optimization of oxide semiconductor thickness through analysis of the surface morphologies can thus contribute to the development of oxide TFT manufacturing technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1654-1659
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• 2014

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1617-1622
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• 2015

This paper analyzes the ratio of tunneling current for channel doping concentration of sub-10 nm asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current in subthreshold region increases in the region of channel length of 10 nm below. Even though asymmetric DGMOSFET is developed to reduce short channel effects, the increase of tunneling current in sub-10 nm is inevitable. As the ratio of tunneling current in off current according to channel doping concentration is calculated in this study, the influence of tunneling current to occur in short channel is investigated. To obtain off current to consist of thermionic emission and tunneling current, the analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for channel doping concentration in sub-10 nm asymmetric DGMOSFET, specially with parameters of channel length, channel thickness, and top/bottom gate oxide thickness and voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.