• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.32-42
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• 2007

The substrate resistance is modeled to estimate the performance degradation of analog circuits by substrate noise in a $0.35{\mu}m$ twin-well non-epitaxial CMOS process. The substrate resistance model equations are applied to the P+ guard-ring isolation structure and a good match was achieved between measurements and models. The substrate resistance is divided into four types and a semi-empirical model equation is obtained for each type of substrate resistance. The rms(root-mean-square) error of the substrate resistance model is below 10% compared with the measured resistance. To apply this substrate resistance model to the P+ guard ring structure, ADS(Advanced Design System) circuit simulation results are compared with the measurement results using Network Analyzer, and relatively good agreements are obtained between measurements and simulations.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.31-39
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• 2021

In this paper, warpage analysis that separates PCB for PoP (Package on Package) into unit and substrate using FEM (Finite Element Method), analysis of the effect of layer thickness on warpage, and SN (Signal-to-Noise) ratio by Taguchi method was carried. According to the analysis result, the contribution of the circuit layer on warpage was very high in the unit PCB, and the contribution of the outer layer was particularly high. On the other hand, the substrate PCB had a high influence of the circuit layer on warpage, but it was relatively low compared to the unit PCB, and the influence of the solder resist was rather increased. Therefore, considering the unit PCB and the substrate PCB at the same time, it is desirable to design the PCB for PoP layer-by-layer structure so that the outer and inner circuit layers are thick, the top solder resist is thin, and the thickness of the bottom solder resist is between 5 ㎛ and 25 ㎛.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1776-1778
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• 2000

The demands placed on portable wireless communication equipment include low cost, low supply voltage, low power, dissipation, low noise, high frequency of operation, and low distortion. These design requirements cannot be met satisfactorily in many cases without the use of RF inductors. However, implementing the inductor on-chip has been regarded as an impractical task because of excessive substrate capacitance and substantial resistive losses due to metallization and the conductive silicon substrate. Hence, there is a great incentive to design, optimize, and model spiral inductors on Si substrate. So, we analyzed a chip inductors using electromagnetic analysis and established a set of design rules for rectangular spiral inductors.

• Journal of Sensor Science and Technology
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• v.24 no.5
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• pp.348-352
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• 2015

Thin nickel oxide films formed on uncooled and cooled $SiO_2/Si$ substrates using a radio frequency (RF) magnetron sputter powered by 200 W in a mixed atmosphere of argon and oxygen. Grazing-incidence X-ray diffraction and field emission scanning electron microscopy are used for the structural analysis of nickel oxide films. The electrical conductivity required for better bolometric performance is estimated by means of a four-point probe system. Columnar and (200) preferred orientations are discovered in both films regardless of substrate cooling. Electric resistivity, however, is greatly influenced by the substrate cooling. Oxygen partial pressure increase during the nickel oxide deposition leads to a rapid decrease in resistivity, and the resistivity is higher in the cooled nickel oxide samples. Even when small microstructure variations are applied, lower resistivity in favor of low noise performance is acquired in the uncooled samples.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.28-31
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• 2004

This paper describe analysis active microstrip antenna with low noise amplifier at 900 MHz for mobile communication. The microstrip patch antenna is integrated with low noise amplifier on a permittivity 4.5 (Epoxy-FR4) and thickness of substrate 1.6 mm. Low noise amplifier is designed by using GaAs FETs. The analysis characteristics of antenna include return loss, input impedance, vswr, radiation pattarn, bandwidth and gain of antenna. Mesurement gain of antenna is shown 19.2435 dBi.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• ETRI Journal
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• v.27 no.5
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• pp.628-634
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• 2005

From AC analysis results utilizing a 2-dimensional device simulator, we extracted an AC-equivalent circuit of a grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.

• Proceedings of the KIEE Conference
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• 2008.10a
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• pp.107-108
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• 2008

This article describes optimization for PGS(Patterned Ground Shield) of rectangular spiral inductor using Taguchi's Design of Experiment. PGS is decrease method of parasite component by silicon substrate among dielectric loss reduction method. Using taguchi's design of experiment, each parameter is fixed upon that PGS high poison(A), slot spacing(B), strip width(C) and overlap turn number(D) of PGS design parameter. Then we verified that percentage contribution and design sensitivity analysis of each parameter and level by signal to noise ratio of larger-the-better type. We consider percentage contribution and design sensitivity of each parameter and level, and then verify that model of optimization for PGS is lower inductance decreasing ratio and higher Q-factor increasing ratio by EM simulation.

• Journal of the Korea Computer Industry Society
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• v.2 no.12
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• pp.1533-1540
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• 2001

In this paper, we described extraction method of electrical parameters and modeling method of PCB nets on PCB design process. To analyze electrical characteristics of real PCB structure, we selected a cache memory system as an experimental board and designed 6 layer PCB substrate. For extraction of the electrical parameters, we divided circuit elements into the components of conductor types which are wires, via holes, BGA balls etc. and combined the calculated value by real net structure to modeling the PCB nets. We analyzed the electrical characteristics of the PCB nets with the simulation tools of SPICE and XNS. The simulation analysis has shown that the maximum signal delay was 2.6ns and the maximum crosstalk noise was 281 mV and we found that the designed substrate was adequate to system specification.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.9
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• pp.1694-1698
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• 2007

This study suggests a new fluorescence microscope to observe micro-samples within fluorophore in a variety of biomedical fields including the fluorescence analysis of a biochip, such as a DNA micro-array. A fluorescence microscope is a device for irradiating light onto a micro-object, executing an excitation and fluorescence emission process. In this study, it adopts a total internal reflection fluorescence(TIRF) method to excite a whole micro-sample substrate different from an existing way which uses an evanescent wave resulting from a total internal reflection on the micro-sample surface. Suggested TIRF microscope can reduce optical noise and obtain images with higher sensitivity thus obtain precise information about the density, quantity, location, etc. of a flurophore, and can simultaneously process separate images even when plurality of fluorophores having different excitation and fluorescent wavelength ranges is distributed, thus easily obtain information about the fluorophores.