• Journal of Software Assessment and Valuation
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• v.16 no.1
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• pp.55-63
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• 2020

Lasers for optical broadband communication systems should have excellent frequency selectivity and modal stability. DFB lasers have low lasing frequency shift during high speed current modulation. In this paper, when a refractive index grating and a gain grating are simultaneously present in a DFB laser having a wavelength of 1.55 ㎛, the dielectric film is coated so that reflection does not occur on the right mirror surface, so that ρ_r=0. For the first mode, which requires a minimum gain at the threshold, the beam distribution of the oscillation mode in the longitudinal direction and the radiated power ratio P_l/P_r were analyzed and compared for the cases of the phase of ρ_l=π and π/2. If the phase of ρ_l=π, in order to obtain a low threshold current and high frequency stability, κL should be greater than 8. In the case of the phase of ρ_l=π/2, for low threshold current, κL is necessary to be 1.0, where the oscillation frequency coincides with the lattice frequency. DFB lasers with an anti-reflection coated mirror have excellent mode selectivity than 1.55um DFB lasers with two mirror facets

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.10
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• pp.811-816
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• 2012

The effect of co-sputtering condition on the structural properties of $Mg_xZn_{1-x}O$ thin films grown by RF magnetron co-sputtering system was investigated for manufacturing ZnO/MgZnO structure LED. $Mg_xZn_{1-x}O$ thin films were grown with ZnO and MgO target varying RF power. Structural properties were investigated by X-ray diffraction (XRD) and Energy dispersive spectroscopy (EDS). The ZnO thin films have sufficient crystallinity on the high RF power. As RF power of ZnO target increased, the contents of MgO in the $Mg_xZn_{1-x}O$ film decreased. LED was manufactured using ZnO/MgZnO multi-layer on p-GaN/$Al_2O_3$ substrate. Threshold voltage of multi-layer LED was appeared at 8 V, and it was luminesced at wave length of 550 nm.

• Journal of IKEEE
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• v.25 no.4
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• pp.770-773
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• 2021

In this paper, the retention characteristics of 3D NAND flash memory applied with tapering and ferroelectric (HfO₂) structure were analyzed after programming operation. Electrons trapped in nitride are affected by lateral charge migration over time. It was confirmed that more lateral charge migration occurred in the channel thickened by tapering of the trapped electrons. In addition, the Oxide-Nitride-Ferroelectric (ONF) structure has better lateral charge migration due to polarization, so the change in threshold voltage (V_th) is reduced compared to the Oxide-Nitride-Oxide (ONO) structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.126-129
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• 2006

We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.79-99
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• 2010

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Journal of Ocean Engineering and Technology
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• v.35 no.5
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• pp.327-335
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• 2021

Microcracks can rapidly grow and develop in high-strength steels used in offshore structures. It is important to render these microcracks harmless to ensure the safety and reliability of offshore structures. Here, the dependence of the aspect ratio (As) of the maximum depth of harmless crack (a_hlm) was evaluated under three different conditions considering the threshold stress intensity factor (Δk_th) and residual stress of offshore structural steel F690. The threshold stress intensity factor and fatigue limit of fatigue crack propagation, dependent on crack dimensions, were evaluated using Ando's equation, which considers the plastic behavior of fatigue and the stress ratio. a_hlm by peening was analyzed using the relationship between Δk_th obtained by Ando's equation and Δk_th obtained by the sum of applied stress and residual stress. The plate specimen had a width 2W = 12 mm and thickness t = 20 mm, and four value of As were considered: 1.0, 0.6, 0.3, and 0.1. The a_hlm was larger as the compressive residual stress distribution increased. Additionally, an increase in the values of As and Δk_th(l) led to a larger a_hlm. With a safety factor (N) of 2.0, the long-term safety and reliability of structures constructed using F690 can be secured with needle peening. It is necessary to apply a more sensitive non-destructive inspection technique as a non-destructive inspection method for crack detection could not be used to observe fatigue cracks that reduced the fatigue limit of smooth specimens by 50% in the three types of residual stresses considered. The usefulness of non-destructive inspection and non-damaging techniques was reviewed based on the relationship between a_hlm, a_NDI (minimum crack depth detectable in non-destructive inspection), a_{cr N} (crack depth that reduces the fatigue limit to 1/N), and As.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1172-1175
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• 2007

We have investigated the threshold voltage shifts(${\Delta}Vth$) and drain current level shift (${\Delta}Ids$) in subthreshold region of a-Si:H TFTs induced by DC Bias (Vgs and Vds) - Temperature stress (BTS) condition. We plotted the transfer curves and the ${\Delta}Vth$ contour maps as Vds-Vds stress bias and Temperature to examine the severe damage cases on TFTs. Also, by drawing out the time-dependent transfer curve (Ids-Vgs) in the region of $10^{-8}\;{\sim}\;10^{-13}$ (A) current level, we can estimate the failure time of TFTs in a operating condition.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.11
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• pp.517-525
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• 2002

The channel region of seep-sub-micrometer MOSFET is non-uniformly doped with pocket implant. Therefore, the advanced threshold voltage model is needed to account for the Short-Channel Effect and Reverse-Short-Channel Effect due to the non-uniform doping concentration in the channel region. In this paper, A scalable analytical model for the MOSFET threshold voltage is developed. The developed model is verified with MEDICI and TSUPREM simulator.