• Korean Journal of Materials Research
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• v.23 no.11
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• pp.631-637
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• 2013

Synthesis of sub-micron $2SnO{\cdot}(H_2O)$ powders by chemical reduction process was performed at room temperature as function of viscosity of methanol solution and molecular weight of PVP (polyvinylpyrrolidone). Tin(II) 2-ethylhexanoate and sodium borohydride were used as the tin precursor and the reducing agent, respectively. Simultaneous calcination and sintering processes were additionally performed by heating the $2SnO{\cdot}(H_2O)$ powders. In the synthesis of the $2SnO{\cdot}(H_2O)$ powders, it was possible to control the powder size using different combinations of the methanol solution viscosity and the PVP molecular weight. The molecular weight of PVP particularly influenced the size of the synthesized $2SnO{\cdot}(H_2O)$ powders. A holding time of 1 hr in air at $500^{\circ}C$ sufficiently transformed the $2SnO{\cdot}(H_2O)$ into $SnO_2$ phase; however, most of the PVP (molecular weight: 1,300,000) surface-capped powders decomposed and was removed after heating for 1 h at $700^{\circ}C$. Hence, heating for 1 h at $500^{\circ}C$ made a porous $SnO_2$ film containing residual PVP, whereas dense $SnO_2$ films with no significant amount of PVP formed after heating for 1 h at $700^{\circ}C$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.21.2-21.2
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• 2009

발광다이오드는 에너지 변환 효율이 높고 친환경적인 장점으로 인하여 차세대 조명용 광원으로 각광받고 있다. 하지만 현재 발광다이오드는 낮은 광추출효율로 인하여 미래의 수요를 충족시킬 수 있을 만큼 충분한 성능의 효율을 나타내지 못하고 있다. 발광다이오드의 낮은 광추출효율은 반도체소재와 외부 공기와의 큰 굴절률 차이로 인하여 발생하는 전반사 현상에 기인한 것으로 이 문제를 해결하기 위하여 발광다이오드 소자의 발광면 및 기판을 텍스처링하는 방법이 중요하게 인식되고 있다. 하지만 현재까지 패턴의 구조에 따른 광추출 특성을 분석한 연구는 미진한 상황이다. 본 연구에서는 임프린팅 및 건식식각 공정을 이용하여 다양한 구조의 나노 및 micron 급 패턴을 발광다이오드의 p-GaN층에 형성하였다. 발광다이오드 기판 위에 하드마스크로 사용하기 위한 SiO2를 50nm 증착한 후 그 위에 UV 임프린팅 공정을 진행하여 폴리머 패턴을 형성시켰다. 임프린팅 공정으로 형성된 폴리머 패턴을 CF4CHF3 플라즈마를 이용하여 SiO2를 건식식각하였고, 이후에 SiCl4와 Ar 플라즈마를 이용한 ICP 식각 공정을 진행하여 p-GaN층을 100nm 식각하였다. 마지막으로 BOE를 이용한 습식식각 공정으로 p-GaN층에 남아있는 SiO2층을 제거하여 p-GaN층에 sub-micron에서 micron급의 홀 패턴을 형성하였다. Photoluminescence(PL) 측정을 통해서 발광다이오드 소자에 형성된 패턴의 구조에 따른 광추출 특성을 분석하였다.

• Proceedings of the Korean Magnestics Society Conference
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• 2003.12a
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• pp.361-361
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• 2003

• Proceedings of the Korean Magnestics Society Conference
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• 2015.11a
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• pp.103-103
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• 2015

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Proceedings of the IEEK Conference
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• 2001.10a
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• pp.633-637
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• 2001

Oil fly ash is known as one source of raw materials from which vanadium and nickel metals can be recovered. The current recovery process of valuable metals from oil fly ash is mainly the hydrormetallurgy one. Nevertheless, a great amount about 50~80%, of unburned carbon remains as byproduct after hydrormetallursy process. In Taiwan, if hydrormetallursy processes have proceeded, it can be estimated that the annual production of unburned carbon is 25 thousand tons. From the viewpoint of resource recycling, this study is a preliminary study and investigates in recovery of sub micron- graphitized carbon from unburned carbon by a designed process. The designed process included the following steps: 1.selecting a portion with +400mesh size from unburned carbon; 2.treating the selected in ultrasonic waves; 3.using a 400mesh sieve to obtain the product which is under 400mesh; 4.Removal ash from the product. In regard to treatment by ultrasonic waves in the designed process, treating time of ultrasonic waves is a simple and only variance in this study. The results indicate that the production yields increase with the treating time of ultrasonic waves; the production yield in specific conditions of this study can reach about 23%, in which ash content in product is about 2.5%. According to results of SEM, TEM and XRD, the products from the designed process are flakes in shape, several microns in size and graphitized carbon in carbon crystal phase. Except to graphitized carbon, there are a little carbon blacks, which are graphite 2H in carbon crystal phase in the products. Conclusively, the designed process is possibly applicable, by which comes to the recovery of micron- graphitized carbon.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.9
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• pp.605-610
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• 2001

Electrostatic comb-drive microactuators with sub-micron gap were fabricated and tested. We designed and fabricated two type of electrodes which are rectangular and triangular tip. The fabricated microactuators with triangular tip resulted in the electrode gaps in the range of 0.55 ${\mu}{\textrm}{m}$~1.35 ${\mu}{\textrm}{m}$ Displacement of 1 ${\mu}{\textrm}{m}$ and electrostatic force of 2.3 $\mu$N were observed in a triangular-tip microactuator with 0.55 ${\mu}{\textrm}{m}$ gap when a DC drive voltage of 13 volts was applied. Measured 1st resonance frequency of microactuators was about 23 kHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.59-65
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• 2014

Two input resistances converted from $S_{11}$-parameter and $Z_{11}$-parameter of MOSFETs with various gate finger numbers Nf were measured in low frequency region. The 1/Nf dependent input resistance from $S_{11}$-parameter exhibits much lower values than that from $Z_{11}$-parameter in the range of $Nf{\leq}64$. This 1/Nf dependence was theoretically verified by using Nf dependent nonlinear equation derived from a MOSFET equivalent circuit.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.