• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.399-402
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• 2007

The effects of heat treatment on the electrical properties of strained-Si/SiGe-on-insulator (SGOI) devices were examined. We proposed the optimized heat treatment processes for improving the back interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA (rapid thermal annealing) before gate oxidation step and the post-RTA after source/drain dopant activation step, the electrical properties of strained-Si channel on $Si_{1-x}Ge_x$ layer were greatly improved, which resulting the improvement of the driving current, transconductance, and leakage current of SGOI-MOSFET.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.695-698
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• 2008

We investigated the characteristics of Strained-Si-on-Insulator (sSOI) MOSFETs with 0.7% tensile strain. The sSOI MOSFETs have superior subthreshold swing under 70 mV/dec and output current. Especially, the electron and hole were increased in sSOI MOSFET. The electron and hole mobility in sSOI MOSFET were 286$cm^2/Vs$ and 151$cm^2/Vs$, respectively. The carrier mobility enhancement is due to the subband splitting by 0.7% tensile strain.

• 대한전자공학회논문지SD
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• 제48권5호
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• pp.12-17
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• 2011

본 연구에서는 $Si_xGe_{1-x}$ 버퍼층 위에 성장된 strained-Si에 Ge 농도에 따라 n-MOSFET를 제작하고 소자 제작 후의 열처리 온도에 따른 소자의 아날로그 성능을 측정 분석하였다. 전자의 유효 이동도는 Ge 농도가 증가함에 따라 증가하였으나 32%로 높을 때에는 열처리 온도에 상관없이 오히려 감소하는 것으로 측정되었다. 상온에서 Ge 농도가 증가함에 따라 증가 소자의 아날로그 성능 지수가 우수하였으나 32% 농도에서는 오히려 좋지 않았다. 고온에서 strained-Si의 전자 유효이동도 저하가 Si보다 심하기 때문 SGOI 소자의 아날로그 성능 저하가 SOI 소자보다 심한 것을 알 수 있었다.

• 한국전기전자재료학회논문지
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• 제11권3호
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• pp.181-187
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• 1998

The ionization energy and degree of ionization for p-type $Si_{1-x}Ge_x$ with boron doping are calculated taking into account the screening and broadening effects. The drift and Hall mobilities are then calculated using the relaxation time approximation and compared with the previously reported measurement data for relaxed and strained $Si_{1-x}Ge_x$ alloys to estimate the alloy scattering potential. From a fit, the alloy scattering potential is found to be 0.5 eV. The in-plane drift mobility for p-type strained $Si_{1-x}Ge_x$ grown on (001) Si substrate is approximately 1+$10x^2$ times higher than that for bulk Si in the high doping range.

• 한국전기전자재료학회논문지
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• 제30권12호
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• pp.757-761
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• 2017

The computational fourier-transform moire (CFTM) method has been briefly explained and this method was used to perform strain analysis of a misfit dislocation in a strained $Si/Si_{0.55}Ge_{0.45}$ layer. An essential advantage of the CFTM method is that it does not require unwrapping, such that errors due to improper unwrapping can be excluded. The analysis results revealed that the Si layer was grown with tensile stress on $Si_{0.55}Ge_{0.45}$ and lattice constant of the Si layer along the growth direction was 1.9% smaller than that of $Si_{0.55}Ge_{0.45}$. On the other hand, strain of the misfit dislocation in the strained $Si/Si_{0.55}Ge_{0.45}$ layer was maximum at the dislocation core due to an extra half-plane and the $e_{xx}$ and $e_{yy}$ values were positive and negative, respectively, along the direction of a burgers vector.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.73-74
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• 2007

We fabricated strained-SOI(sSOI) n-/p-MOSFETs and investigated the electron/hole mobility characteristics. The subthreshold characteristics of sSOI MOSFETs were similar to those of conventional SOI MOSFET. However, The electron mobility of sSOI nMOSFETs was larger than that of the conventional SOI nMOSFETs. These mobility enhancement effects are attributed to the subband modulation of silicon conduction band.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.130-130
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• 2011

최근 반도체 메모리 산업의 발전과 동시에 발생되는 문제들을 극복하기 위한 새로운 기술들이 요구되고 있다. DRAM (dynamic random access memory) 의 경우, 소자의 크기가 수십 나노미터 영역으로 줄어들면서, 단채널 효과에 의한 누설전류와 소비전력의 증가 등이 문제가 되고 있다. 하나의 캐패시터와 하나의 트랜지스터로 구성된 기존의 DRAM은, 소자의 집적화가 진행 되어 가면서 정보저장 능력이 감소하는 것을 개선하기 위해, 복잡한 구조의 캐패시터 영역을 요구한다. 이에 반해 하나의 트랜지스터로 구성되어 있는 1T-DRAM의 경우, 캐패시터 영역이 없는 구조적인 이점과, SOI (silicon-on-insulator) 구조의 기판을 사용함으로써 뛰어난 전기적 절연 특성과 기생 정전용량의 감소, 그리고 기존 CMOS (complementary metal oxide semiconductor) 공정과의 호환성이 장점이다. 또한 새로운 물질 혹은 구조를 적용하여, 개선된 전기적 특성을 통해 1T-DRAM의 메모리 특성을 향상 시킬 수 있다. 본 연구에서는, SOI와 SGOI (silicon-germanium-on-insulator) 및 sSOI (strained-si-on-insulator) 기판을 사용한 MOSFET을 통해, strain 효과에 의한 전기적 특성 및 메모리 특성을 평가 하였다. 그 결과 strained-Si층과 relaxed-SiGe층간의 tensile strain에 의한 캐리어 이동도의 증가를 통해, 개선된 전기적 특성 및 메모리 특성을 확인하였다. 또한 채널층의 결함이 적은 sSOI 기판을 사용한 1T-DRAM에서 가장 뛰어난 특성을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.7-8
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• 2006

The effects of heat treatment on the electrical properties of SGOI were examined. We proposed the optimized heat treatments for improving the interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA(rapid thermal annealing) before gate oxidation and post-RTA after dopant activation, the driving current, the transconductance, and the leakage current were improved significantly.

• ETRI Journal
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• 제43권5호
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• pp.909-915
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• 2021

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer-scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3-㎛ bowing was observed using the 725-㎛-thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4×10⁷ cm^-2. For lattice-matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725-㎛-thick Si substrate can be used for the large-scale integration of GaAs on Si with less bowing and low TDD.