• 대한전자공학회논문지SD
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• 제42권7호
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• pp.37-44
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• 2005

본 논문은 보드 또는 SoC 상에서 코아와 코아 사이의 연결선 고장 점검을 위한 효과적인 테스트 패턴 알고리즘과 테스트 패턴 생성기를 소개한다. 연결선 고장 모델 분석을 통해 crosstalk과 정적인 고장을 100$\%$ 점검할 수 있는 6n 패턴 알고리즘을 소개한다 보다 적은 4n+1 개의 패턴으로 100\$\%$에 가까운 고장 점검율을 얻으면서 crosstalk 뿐 아니라 정적고장의 검출 및 진단도 가능한 알고리즘을 제안하고, 효과적인 BIST구현 기술에 대하여 소개한다.

• 한국지능시스템학회논문지
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• 제26권2호
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• pp.135-140
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• 2016

비동기 순차 회로를 위한 교정 제어기는 회로를 재설계하지 않고도 회로 내에 존재하는 여러 고장을 탐지하고 극복하는 능력을 보인다. 이번 논문에서는 교정 제어기의 크기를 줄이기 위한 방법으로서 정적 교정 제어기(static corrective controller)를 제안한다. 동적 제어기에 비해 정적 제어기는 제어기 상태가 필요 없으므로 조합 회로(combinational circuit)만으로 구현 가능하다. 본 논문에서는 상태 천이 고장에 대한 정적 내고장성 교정 제어기가 존재할 조건과 설계 과정을 규명한다. 또한 제안된 제어 기법을 FPGA로 구현된 SEU 오류 카운터에 적용하여 그 효용성을 실험적으로 검증한다.

• 대한임베디드공학회논문지
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• 제13권6호
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• pp.305-312
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• 2018

Software has been used to develop many functions of the modern weapon systems which has a high mission criticality. Weapon system software must consider multi-threaded processing to satisfy growing performance requirement. However, developing multi-threaded programs are difficult because of concurrency faults, such as unintended data races. Especially, it is important to prepare analysis for debugging the data races, because the weapon system software may cause personal injury. In this paper, we present an efficient framework of analysis, called ConDeWS, which is designed to determine the scope of dynamic analysis through using the result of static analysis and fault analysis. As a result of applying the implemented framework to the target software, we have detected unintended data races that were not detected in the static analysis.

• E2M - 전기 전자와 첨단 소재
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• 제10권4호
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• pp.349-354
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• 1997

This paper aims at studying the improvement of test method for t-weight sensitive fault (t-wsf) detect. The development of RAM fabrication technology results in not only the increase at device density on chips but also the decrease in line widths in VLSI. But, the chip size that was large and complex is shortened and simplified while the cost of chips remains at the present level, in many cases, even lowering. First of all, The testing patterns for RAM fault detect, which is apt to be complicated , need to be simplified. This new testing method made use of Local Lower Bound (L.L.B) which has the memory with the beginning pattern of 0(l) and the finishing pattern of 0(1). The proposed testing patterns can detect all of RAM faults which contain stuck-at faults, coupling faults. The number of operation is 6N at 1-weight sensitive fault, 9,5N at 2-weight sensitive fault, 7N at 3-weight sensitive fault, and 3N at 4-weight sensitive fault. This test techniques can reduce the number of test pattern in memory cells, saving much more time in test, This testing patterns can detect all static weight sensitive faults and pattern sensitive faults in RAM.

• 한국정밀공학회지
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• 제19권4호
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• pp.168-178
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• 2002

The CNC machine toots has two kinds of fault. One is the fault due to degraded parts and the other is the fault due to operation disability. The phenomena of degradation is predictable but the operational fault is unpredictable because it occurred without any warning. The major faults of CNC machine tool are operational faults which are charged over 70%. This paper describes the model of remote service and the intelligent fault diagnosis system to diagnosis operational faults of CNC machine tools. To generalize fault diagnosis, two diagnosis models such as SF(Switching Function) and SSF(Step Switching Function) are proposed. The SF is static model and SSF is dynamic model for expression of fault. The SF and SSF model can be generated using SFG(Switching Function Generator) which is developed in this research. The three major operational faults such as emergency stop error, cycle start disability and machine ready disability are applied to experiment of fault modeling. To remote service of faults fur CNC machine tool, the web server and client system based internet are proposed as the suitable environment. The developed two technologies are implemented with the internal function of open architecture controller. The implemental results for two technologies are presented to validate the proposed scheme.

• 한국정보과학회논문지:시스템및이론
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• 제26권8호
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• pp.1024-1030
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• 1999

IEEE 1149.1 바운다리스캔은 보드 수준에서 고장점검 및 진단을 위한 테스트 설계기술이다. 그러나, 바운다리스캔 제어기의 특성상 테스트 패턴의 주입에서 관측까지 2.5 TCK가 소요되므로, 연결선상의 지연고장을 점검할 수 없다. 본 논문에서는 UpdateDR 신호를 변경하여, 테스트 패턴 주입에서 관측까지 1 TCK가 소요되게 함으로써, 지연고장 점검을 가능하게 하는 기술을 소개한다. 나아가서, 정적인 고장점검을 위한 테스트 패턴을 개선해 지연고장 점검까지 가능하게 하는, N개의 net에 대한 2 log(n+2) 의 새로운 테스트패턴도 제안한다. 설계와 시뮬레이션을 통해 지연고장 점검이 가능함을 확인하였다.Abstract IEEE 1149.1 Boundary-Scan is a testable design technique for the detection and diagnosis of faults on a board. However, since it takes 2.5TCKs to observe data launched from an output boundary scan cell due to inherent characteristics of the TAP controller, it is impossible to test delay defects on the interconnect nets. This paper introduces a new technique that postpones the activation of UpdateDR signal by 1.5 TCKs while complying with IEEE 1149.1 standard. Furthermore we have developed 2 log(n+2) , where N is the number of nets, interconnect test patterns to test delay faults in addition to the static interconnect faults. The validness of our approach is verified through the design and simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.182-184
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• 2006

A down-scaled simulator is developed to simulate typical faults in induction motor such as short-turn stator winding, broken rotor bar, dynamic and static air-gap eccentricity, bearing trouble, and mechanical unbalance. The simulator is used as an initial builder to develop design algorithm for real-time faults detecting system by processing an abnormal signal and characteristics in each fault.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.23-25
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• 1996

In this paper aims at studying the minimal test pattem of the RAM. This also propose a scheme of testing faults from the new fault model using the LLB. The length of test patterns are 6N(1-wsf), 9.5N(2-wsf), 7N(3-wsfl, 3N(4-wsf) operations in N-bit RAM. This test techniques can write into memory cell the number of write operations is reduced and then much testing time is saved. A test set which detects all positive-negative static t-ws faults for t=0, 1, 2, 3, 4 and detects all pattern sensitive fault in memory array. A new fault model, which encompasses the existing fault model Is proposed.

• 전자공학회논문지A
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• 제30A권11호
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• pp.140-148
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• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

• 제어로봇시스템학회논문지
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• 제13권12호
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• pp.1147-1152
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• 2007

This paper deals with a scheme for fault-tolerance improvement of real-time embedded systems, which engages an equidistant checkpointing technique to tolerate transient errors. Transient errors are caused by transient faults which are the most significant type of fault in reliable computer systems. Transient faults are assumed to occur according to a Poisson process and to be detected in a non-concurrent manner (e.g., checked periodically). The probability of the successful real-time task completion in the presence of transient errors is derived with the consideration of the possible effects of the transient errors. Based on this, a condition under which inserting checkpoints improves the fault-tolerance of the system is introduced and an optimal equidistant checkpointing strategy that achieves the highest fault tolerance is presented.