• Journal of Elementary Mathematics Education in Korea
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• v.18 no.1
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• pp.105-122
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• 2014

In this paper, fraction division algorithms in Korean elementary mathematics textbooks are analyzed as a part of the groundwork to improve teaching methods for fraction division algorithms. There are seemingly six fraction division algorithms in ${\ll}Math\;5-2{\gg}$, ${\ll}Math\;6-1{\gg}$ textbooks according to the 2006 curriculum. Four of them are standard algorithms which show the multiplication by the reciprocal of the divisors modally. Two non-standard algorithms are independent algorithms, and they have weakness in that the integration to the algorithms 8 is not easy. There is a need to reconsider the introduction of the algorithm 4 in that it is difficult to think algorithm 4 is more efficient than algorithm 3. Because (natural number)${\div}$(natural number)=(natural number)${\times}$(the reciprocal of a natural number) is dealt with in algorithm 2, it can be considered to change algorithm 7 to algorithm 2 alike. In textbooks, by converting fraction division expressions into fraction multiplication expressions through indirect methods, the principles of calculation which guarantee the algorithms are explained. Method of using the transitivity, method of using the models such as number bars or rectangles, method of using the equivalence are those. Direct conversion from fraction division expression to fraction multiplication expression by handling the expression is possible, too, but this is beyond the scope of the curriculum. In textbook, when dealing with (natural number)${\div}$(proper fraction) and converting natural numbers to improper fractions, converting natural numbers to proper fractions is used, but it has been never treated officially.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1044-1051
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• 2020

The age of quantum computers is coming soon. In order to prepare for the upcoming future, the National Institute of Standards and Technology has recruited candidates to set standards for post quantum cryptography to establish a future cryptography standard. The submitted ciphers are expected to be safe from quantum algorithm attacks, but it is necessary to verify that the submitted algorithm is safe from quantum attacks using quantum algorithm even when it is actually operated on a quantum computer. Therefore, in this paper, we investigate an efficient quantum gate implementation for binary field multiplication of code based post quantum cryptography to work on quantum computers. We implemented the binary field multiplication for two field polynomials presented by Classic McEliece and three field polynomials presented by ROLLO in generic algorithm and Karatsuba algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• Journal of Korea Multimedia Society
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• v.6 no.4
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• pp.610-619
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• 2003

This paper presents a concept of cellular automata and a modular exponentiation algorithm and implementation of a basic EIGamal encryption by using cellular automata. Nowadays most of modular exponentiation algorithms are implemented by a linear feedback shift register(LFSR), but its structure has disadvantage which is difficult to implement an operation scheme when the basis is changed frequently The proposed algorithm based on a cellular automata in this paper can overcome this shortcomings, and can be effectively applied to the modular exponentiation algorithm by using the characteristic of the parallelism and flexibility of cellular automata. We also propose a new fast multiplier algorithm using the normal basis representation. A new multiplier algorithm based on normal basis is quite fast than the conventional algorithms using standard basis. This application is also applicable to construct operational structures such as multiplication, exponentiation and inversion algorithm for EIGamal cryptosystem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7A
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• pp.547-556
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• 2003

This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.40-47
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• 2006

The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.41-47
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• 2016

The times of multiplication for encryption and decryption of cryptosystem is primarily determined by implementation efficiency of the modular exponentiation of $a^b$(mod m). The most frequently used among standard modular exponentiation methods is a standard binary method, of which n-ary($2{\leq}n{\leq}6$) is most popular. The n-ary($1{\leq}n{\leq}6$) is a square-and-multiply method which partitions $b=b_kb_{k-1}{\cdots}b_1b_{0(2)}$ into n fixed bits from right to left and squares n times and multiplies bit values. This paper proposes a variable-length partition algorithm that partitions $b_{k-1}{\cdots}b_1b_{0(2)}$ from left to right. The proposed algorithm has proved to reduce the multiplication frequency of the fixed-length partition n-ary method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.5 s.305
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• pp.137-144
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• 2005

In this paper, the extraction method of the edge histogram directly using wavelet coefficients in the wavelet domain for JPEG2000 images is proposed. MPEG-7 Edge Histogram Descriptor(EHD) extracts edge histogram in the spacial domain. This algorithm has much multiplication and addition for the edge extraction because it needs the decoding processing. However because the proposed algorithm extracts the edge histogram in the wavelet domain, it doesn't need the decoding processing and it decreases multiplication and addition. The Discrete Wavelet Transform(DWT) is a standard transform in JPEG2000. The proposed algorithm uses Le Gall 5/3 filter in JPEG2000 and odd coefficients in LH2 and HL2 sub-band. The edge direction can be decided to use rate of HL2 and LH2 odd coefficients. According to experiments, there is no difference of the efficiency between EHD and the proposed algorithm And the proposed algorithm is much better than EHD for multiplication and addition in the edge extraction of images.