• International Journal of Contents
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• v.2 no.1
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• pp.34-38
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• 2006

In this paper, an overview of anti-collision algorithm for RFID system of a standard EPC Class1 protocol is presented, and the binslotted dynamic search algorithm (BDS) based upon the slotted ALOHA and binary tree procedure is proposed and analyzed. Also, the performance is evaluated as comparing the BDS algorithm with the standard bin-slotted algorithm (BSA) through the simulation program. The performance of the proposed BDS algorithm is improved by dynamically identifying the collided-bit position and the collided bins stored in the stack of the reader. As the results, the number of request command that a reader send to tags in the reader s interrogation zone and the total recognition time are decreased to 59% as compared with BSA algorithm. Therefore, the tag identification performance is fairly improved by resolving a collision problem using the proposed BDS algorithm.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.1
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• pp.61-69
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• 2002

This paper describes a converting algorithm between programmable languages of a software PLU. It is based on IEC 61131-3 standard and PC. The proposed control logic is designed by the software model and common element with data type, variables, POUs(program organization unit) and execution control unit commonly used within programmable languages of IEC 61131-3 Standard. The generation method of object file is proposed on five programmable language based on IEC 61131-3. It is represented as fo11ows; 1) the generation method using conversion algorithm from LD to IL with FBD(function block diagram), 2) the generation method using f code generation algorithm from SFC using the SFC execution sequence with FBD and ST(structured text). The proposed control logic generator was implemented by Visual C++ 6.0 and MFC on MS-windows NT 4.0.

• Journal of Satellite, Information and Communications
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• v.7 no.3
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• pp.47-53
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• 2012

In this paper, we present an algorithm called redundant logical paths (RLP) for efficient HSR traffic reduction. It creates redundant logical paths between each HSR node and all the other nodes. Eventually, a logical full-meshed network or paths will be established among all HSR node types, except the Quadbox type, which is used only for interconnection. The logical full-meshed network will be used instead of using the standard HSR protocol that depends on the concepts of the duplication and forwarding of the received frame until it reaches the destination node. The RLP algorithm results in significantly less frame traffic because there is no random forwarding as in the standard HSR protocol. For the sample network in this paper simulation results showed a 61.5-80% reduction in network frame traffic compared to the standard HSR. Our algorithm will avoid latency issues in the network and even network congestion, thus improving network efficiency.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.1
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• pp.37-44
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• 2011

HSPA(High Speed Packet Access)/HSPA+ is a combined 3GPP(Third Generation Partnership Project) standard of HSDPA(High Speed Downlink Packet Access) and HSUPA(High Speed Uplink Packet Access). The standard can provide the high speed multimedia service against the 3GPP release 99 standard. In order to test the 3GPP HSPA/HSPA+ terminal performance, the measurement hardware is required for the evaluate the transmitted signal of HSPA/HSPA+ terminals. Agilent Technologies and Innowireless produce the measurement equipments for HSPA/HSPA+ terminals. Generally speaking, the receiving algorithms in normal modems cannot be used directly to the measurement system due to the lack of the algorithm accuracy. In this paper, we propose the new receiver algorithm for precise measurement of 3GPP HSPA/HSPA+ terminal signal, and implement measurement functionality for performance measurement of the 3GPP HSPA/HSPA+ terminal by using software. The proposed 3GPP HSPA/HSPA+ signal measurement algorithm can be used for the commercial system through code execution speed optimization.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.9
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• pp.4448-4466
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• 2018

In recent years, due to its high efficiency and better performance, the high efficiency video coding (HEVC) has become the most common compression standard in the field of video coding. In this paper, the framework of HEVC is deeply analyzed, and an improved HEVC video coding algorithm based on all phase biorthogonal transform (APBT) is proposed, where APBT is utilized to replace the discrete cosine transform (DCT) and discrete sine transform (DST) in original HEVC standard. Based on the relationship between APBT and DCT, the integer APBT is deduced. To further improve the coding performance, an optimal HEVC video coding algorithm based on hybrid APBT is proposed. The coding performance of the proposed HEVC coding algorithm is improved without increasing the complexity. Experimental results show that compared with HEVC standard algorithm, the improved HEVC video coding algorithm based on hybrid APBT can improve the coding performance of chrominance components by about 0.3%.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.708-711
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• 1999

MDCT( Modified Discrete Cosine Transform ) is one of the most compute-intensive operations in the MPEG audio coding standard. In this paper a fast algorithm to perform MDCT operation is presented. The algorithm presented in the MPEG audio coding standard requires (N/2) $\times$ N multiplications and (N/2) $\times$ (N-1) additions to generate the result, but the algorithm presented in this paper requires (N/2) $\times$ (N/2) multiplications and (N/2) $\times$ (N/2) additions to perform the same task. In this algorithm N should be multiple of 4. The algorithm was implemented using ARM processor and the processing time comparison between the original algorithm and the fast algorithm is presented.

• ETRI Journal
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• v.44 no.5
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• pp.837-848
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• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.116-120
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• 1999

The step response of the Manabe standard form[1］has little overshoot and shows almost same waveforms regardless of the order of the characteristic polynomials. In some situations it is difficult to control the rise time and settling time simultaneously of the step response of the Manabe standard form. To control its rise time and settling time efficiently, we develop the generalization of the Manabe standard form: we try to find out the SRFS(Slow Rise time & Fast Settling time) form which has the slower rise time and faster settling time than those of the Manabe standard form. we also consider the other three forms: FRSS(Fast Rise time & Slow Settling time), SRFS(Slow Rise time ＆ Fast Settling time) and SRSS(Slow Rise time & Slow Settling time) forms. In this paper, by using the genetic algorithm, we obtain all the coefficient of the four forms we mention above. Finally, we design a controller for a given plant so that the overall system has the performance that the rise time is faster, the settling time is slower than those of the Manabe standard form.

• Journal of the Korean Society of Visualization
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• v.4 no.2
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• pp.37-43
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• 2006

An experimental apparatus for PIV performance evaluation has been developed. Stardard uncertainty of a two-dimensional cross-correlation PIV system was investigated based upon the standard experimental apparatus, which was devised to model the rigid body rotating flows. For the systematic analysis of the uncertainty introduced by each component (algorithm, CCD camera, frame grabber) of the PIV system, standard images are fed into the component independently. The standard experiments show that 53% of the uncertainty in the present PIV system results from the frame grabber but the errors from the algorithm and digital camera are ignorable.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.218-221
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• 2000

In this paper, we propose a new algorithm to detect human faces for controling a camera used in video conference. We model the distribution of skin color and set up the standard skin color in YIQ color space. An input video frame image is segmented into skin and non-skin segments by comparing the standard skin color and each pixels in the input video frame. Then, shape filler is applied to select face segments from skin segments. Our algorithm detects human faces in real time to control a camera to capture a human face with a proper size and position.