• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2001년도 추계학술대회논문집 II
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• pp.866-870
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• 2001

Measurement techniques for in-duct acoustic source parameters can be classified into the direct method and the load method, according to whether it utilizes an extra external source or not. It is reported that the load methods yield the negative source resistance and the purpose of this paper is to clarify that the time-varying nature of the source is the main cause of this physically implausible result. For this purpose, the direct and load methods for measuring the source characteristics of a simplified fluid machine are simulated using the time domain numerical analysis. In the numerical simulations, the method of characteristics is employed and the source characteristics are calculated from the resultant data. It is shown that the load method results in negative source resistance for some frequencies, whereas the direct method yields positive values for all frequencies considered. It is found that the result of load method is quite sensitive to the change of cylinder pressure or valve profile in contrast to the direct method.

• 한국태양에너지학회 논문집
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• 제29권5호
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• pp.20-27
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• 2009

The effect of borehole thermal resistance on the borehole length is studied. In performing this work a new concept BLRR(borehole length reduction rate) is developed based on the line source model. The solution of line source model is shown to be valid through the comparison with the data of thermal response test. It is shown that BLRR is a function of soil thermal conductivity(k) and borehole thermal resistance($R_b$). The value of BLRR increases with increasing k, which means reducing $R_b$ is more effective when k is high. The reduction of borehole length with change of $R_b$ is easily estimated with BLRR. The validity of BLRR is also examined with EED analysis.

• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.533-536
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• 1998

The electrical characteristics of NMOSFETs with asymmetrical source/drain regions have been expermentally investigated using test devices fabricated by $0.35\mu\textrm{m}$ CMOS technology. The performance degradation for asymmetric transistor and its causes are analyzed. The parasitic resistances, such as series resistance of active regions and silicide junction contact resistance, are distributed in parallel along the channel. Depending on source/drain geometry, the array of those resistances is changed, that results the various electrical properties.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.144-146
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• 1998

In this study Dead time equivalent resistance of Voltage source power converter is very important in current controller design. And Non-linear Modeling method can be applied in Power converter analysis. Using Describing Function method and Non-linear Resistance Modeling. Voltage Source Power Converter Bode diagram and Current controller analysis method are more reality.

• 한국생산제조학회지
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• 제20권2호
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• pp.162-168
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• 2011

In this research, nitrogen plasma source ion implantation(PSII) of non-coated tungsten carbide endmill tools was conducted with low heat treatment for increasing wear resistance. After the low heat treatment of PSIIed tools to give a homogeneity of wear resistance, the surface modification of tools was analyzed by hardness test, surface roughness and cutting forces. As for the resultant cutting forces, low heat treatment in temperature of $400^{\circ}C$ and $500^{\circ}C$ is stable because of low cutting resistance. The 20-minutes heat treated tool at spindle speed 25000rpm has superiority of surface roughness, Ra of $0.420{\mu}m$ and was found to have good wear resistance. The higher hardness value was obtained by increasing temperature from $300^{\circ}C$ to $600^{\circ}C$ for PSIIed tools with low heat treatment. As the PSIIed tools under 10minutes at temperature of $600^{\circ}C$ have the highest hardness as Hv of 2349.8, It was analyzed that temperature processing give much influences on hardness.

• 한국태양에너지학회 논문집
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• 제30권4호
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• pp.71-78
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• 2010

Investigation of the effective soil thermal conductivity(k) is the first step in designing the ground loop heat exchanger(borehole) of a geothermal heat pump system. The line source method is required by New and Renewable Energy Center of Korea Energy Management Corporation in analyzing data obtained from thermal response tests. Another important factor in designing the ground loop heat exchanger is the borehole thermal resistance($R_b$). There are two methods to evaluate $R_b$ : one is to use a line source method, and the other is to use a shape factor of the borehole. In this study, we demonstrated that the line source method produces better results than the shape factor method in evaluating $R_b$. This is because the borehole thermal resistance evaluated with the line source method characteristically reduces the temperature differences between an actual and a theoretical thermal behaviors of the borehole. Evaluation of $R_b$ requires soil volumetric heat capacity. However, the effect of the soil volumetric heat capacity on the borehole thermal resistance is very small. Therefore, it is possible to use a generally accepted average value of soil volumetric heat capacity($=2MJ/m^3{\cdot}K$) in the analysis. In this work, it is also shown that an acceptable range of the initial ignoring time should be in the range of 8~16hrs. Thus, a mean value of 12 hrs is recommended.

• 전자공학회논문지
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• 제53권8호
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• pp.39-48
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• 2016

본 논문에서는 소스와 드레인의 구조가 육각형인 FinFET에서 구조 변수 및 핀/핑거 개수 증가에 따른 열 저항 모델을 제안한다. 소자의 크기가 감소하여 발열 효과 및 열 특성의 영향이 커졌으며, 이를 분석하기 위해 소자의 열 저항은 중요한 요소이다. 열 저항 모델은 소자에서 열이 생성되는 열원과 열이 빠져나가는 contact를 설정했으며, 도메인은 열원과 4 부분의 소스, 드레인, 게이트, 서브스트레이트 contact를 통해 나누어진다. 또 각각의 contact 열 저항 모델은 TCAD의 시뮬레이션 결과의 온도 및 열 흐름을 분석하여 해석이 용이한 형태로 세분화하였다. 도메인들은 그 구조에 따라 구조 변수를 통한 적분 및 등각 매핑 방식을 기반으로 모델링하였다. 먼저 싱글 핀으로 열 저항을 분석하여 모델링하였으며, 멀티 핀/핑거의 열 저항 모델의 정확도를 높이기 위해 채널증가에 따른 파라미터의 변화를 적용하였다. 제안한 열 저항 모델은 3D Technology CAD 시뮬레이션을 해석하여 얻은 열 저항 결과와 비교하였으며, 싱글 핀 및 멀티 핀의 전체 열 저항 모델은 3 % 이하의 오차를 얻었다. 제안한 열 저항은 핀/핑거 개수의 증가에 따른 열 저항을 예측할 수 있으며, 발열효과 및 열 특성 분석을 계산하여 회로 특성을 개선할 수 있다.

• 대한조선학회논문집
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• 제53권4호
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• pp.329-335
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• 2016

In the present paper, Computational fluid dynamics (CFD) uncertainty analysis proposed by ITTC was investigated and applied to ship resistance performance using open source libraries, called OpenFOAM. Uncertainties for grid size, time step and iteration number were studied. Wave patterns and hull wave profile were compared for various uncertainty parameters. From results, grid size uncertainty was mainly contributed to simulation numerical uncertainty.