• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.133-133
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• 2008

Recently, as the down-scailing of field-effect transistor devices continues, Schottky-barrier field-effect transistors (SB-FETs) have attracted much attention as an alternative to conventional MOSFETs. SB-FETs have advantages over conventional devices, such as low parasitic source/drain resistance due to their metallic characteristics, low temperature processing for source/drain formation and physical scalability to the sub-10nm regime. The good scalability of SB-FETs is due to their metallic characteristics of source/drain, which leads to the low resistance and the atomically abrupt junctions at metal (silicide)-silicon interface. Nevertheless, some reports show that SB-FETs suffer from short channel effect (SCE) that would cause severe problems in the sub 20nm regime.[Ouyang et al. IEEE Trans. Electron Devices 53, 8, 1732 (2007)] Because source/drain barriers induce a depletion region, it is possible that the barriers are overlapped in short channel SB-FETs. In order to analyze the SCE of SB-FETs, we carried out systematic studies on the Schottky barrier overlapping in short channel SB-FETs using a SILVACO ATLAS numerical simulator. We have investigated the variation of surface channel band profiles depending on the doping, barrier height and the effective channel length using 2D simulation. Because the source/drain depletion regions start to be overlapped each other in the condition of the $L_{ch}$~80nm with $N_D{\sim}1\times10^{18}cm^{-3}$ and $\phi_{Bn}$ $\approx$ 0.6eV, the band profile varies as the decrease of effective channel length $L_{ch}$. With the $L_{ch}$~80nm as a starting point, the built-in potential of source/drain schottky contacts gradually decreases as the decrease of $L_{ch}$, then the conduction and valence band edges are consequently flattened at $L_{ch}$~5nm. These results may allow us to understand the performance related interdependent parameters in nanoscale SB-FETs such as channel length, the barrier height and channel doping.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1409-1418
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• 1990

Characteristics of NMOS transistors with phosphorus source/drain junctions formed by two-step rapid thermal diffusion (RTD) process using a solid diffusion source have been investigated. Phosphorus profiles after RTD were measured by SIMS analysis. In the case of 1100\ulcorner, 10sec RTD of, P, the specific contact resistance of n+ Si-Al was 2.4x10**-7 \ulcorner-cm\ulcorner which is 1/5 of the As junction The comparison fo P junction devices formed by RTD and conventional As junction devices shows that both short channel effect and hot carrier effect of P junction devices are smaller than those of As junction devices when the devices have same junction depths. P junction device had maximum of 0.4 times lower Isub/Id than As junction device. Characteristics of P junction formed by several different RTD conditions have been compared and 1000\ulcorner RTD sample had the smaller hot carrier generation. Also, it has been shown that the hot carrier generation can be futher reduced by forming the P junctions by 3-step RTD which has RTO-driven-in process additionally.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.648-650
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• 2008

We used micro-contact printing for source and drain electrodes of OTFTs. The proper solvent of Ag paste and baking temperature were extracted for PVP gate dielectric and pentacene semiconductor. The mobility was 0.025 cm2/V.sec and on/off ratio was $2{\times}10^5$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.159-165
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• 1995

A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.263-266
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• 2003

The gate leakage current is first calculated using the experimental method between gate and drain by opening source electrode. Next, the gate to drain current has been obtained with a ground source. The difference of two current has been tested and provide that the existence of another source to Schotuy barrier height against the image force lowering effect.

• Proceedings of the Korean Geotechical Society Conference
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• 2000.03b
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• pp.223-230
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• 2000

Sand drain as a vertical drainage is widely used in soft ground improvement. Recently, sand, the principal source of sand drain, is running out. The in-situ tests were carried out to utilize gravel as a substitute for sand. In-situ tests area was divided into two areas by material used. One is Sand Drain(SD) and Sand Compaction Pile(SCP) area, the other is Gravel Drain(GD) and Gravel Compaction Pile(GCP) area. Both areas were monitored to obtain the information on settlement, pore water pressure and bearing capacity by measuring instruments for stage loading caused by embankment. The results of measurements were analyzed, The clogging effect was checked at various depth in gravel column after the test. According to the test results, the settlement was found to be smaller in gravel drain than in sand drain. The increase in bearing capacity by gravel pile explains the result. The clogging effect was not found in gravel column. It is assumed that gravel is relatively acceptable as a drainage material. Gravel is considered to be a better material than sand for bearing capacity, and it is found that bearing capacity is larger when gravel is used as a gravel compaction pile than as a gravel drain.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.6
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• pp.951-957
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• 1994

We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.112-120
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• 1996

With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.97-98
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• 2006

High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.