• 제목/요약/키워드: source/drain

검색결과 578건 처리시간 0.032초

Fabrication of 1-${\mu}m$ channel length OTFTs by microcontact printing

  • Shin, Hong-Sik;Baek, Kyu-Ha;Yun, Ho-Jin;Ham, Yong-Hyun;Park, Kun-Sik;Lee, Ga-Won;Lee, Hi-Deok;Wang, Jin-Suk;Lee, Ki-Jun;Do, Lee-Mi
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.1118-1121
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    • 2009
  • We have fabricated inverted staggered pentacene Thin Film Transistor (TFT) with 1-${\mu}m$ channel length by micro contact printing (${\mu}$-CP) method. Patterning of micro-scale source/drain electrodes without etching was successfully achieved using silver nano particle ink, Polydimethylsiloxane (PDMS) stamp and FC-150 flip chip aligner-bonder. Sheet resistance of the printed Ag nano particle films were effectively reduced by two step annealing at $180^{\circ}C$.

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Organic thin-film transistors and transistor diodes with transfer-printed Au electrodes

  • Cho, Hyun-Duck;Lee, Min-Jung;Yoon, Hyun-Sik;Char, Kook-Heon;Kim, Yeon-Sang;Lee, Chang-Hee
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.1122-1124
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    • 2009
  • Organic thin-film transistors (OTFTs) were fabricated by using the transfer patterning method. In order to remove Au pattern easily, UV-curable polymer mold was surface treated. Au source/drain (S/D) pattern was transferred to insulator-coated substrate surface. Fabricated OTFTs were compared to OTFTs using vacuum-deposited Au S/D. Additionally, transistor diodes were characterized.

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Self sustained n-type memory transistor devices based on natural cellulose paper fibers

  • Martins, R.;Barquinha, P.;Pereira, L.;Goncalves, G.;Ferreira, I.;Fortunato, E.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.1044-1046
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    • 2009
  • Here we report the architecture for a non-volatile n-type memory paper field-effect transistor. The device is built using the hybrid integration of natural cellulose fibers (pine and eucalyptus fibers embedded in an ionic resin), which act simultaneously as substrate and gate dielectric, with amorphous GIZO and IZO oxides as gate and channel layers, respectively. This is complemented by the use of continuous patterned metal layers as source/drain electrodes.

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High performance OTFT using PEDOT:PSS on plastic substrate by inkjet printing

  • Lee, Myung-Won;Choi, Jae-Chul;Park, Jong-Seung;Song, Chung-Kun
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.874-876
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    • 2009
  • This is a report on fabrication and electrical characteristics of pentacene OTFT that uses conducting PEDOT/PSS as source drain electrodes. We demonstrate enhanced conductivity of PEDOT/PSS film with glycerol and optimize properties for ink jet printing. We also present the application of oxygen plasma technique in order to favor selective spreading for subsequent inkjet printing.

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Investigation of charge injection in organic thin film transistor using ink-jet printed silver electrodes

  • Kim, Dong-Jo;Jeong, Sun-Ho;Lee, Sul;Jang, Dae-Hwan;Moon, Joo-Ho
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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    • pp.730-732
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    • 2007
  • We fabricated a coplanar type organic thin-film transistors using ink-jet printed silver source/drain electrodes and ${\alpha},{\omega}-dihexylquaterthiophene$ (DH4T) which is an active layer. Use of ink-jet printed silver nanoparticle-based metal electrode assists the energetic mismatch with p-type organic semiconductor via modification of their interfacial properties to enable ohmic contact formation.

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Dual Gate-Controlled SOI Single Electron Transistor: Fabrication and Coulomb-Blockade

  • Lee, Byung T.;Park, Jung B.
    • Journal of Electrical Engineering and information Science
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    • 제2권6호
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    • pp.208-211
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    • 1997
  • We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.

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전력 TFT 소자의 제작과 전기적인 특성 (Fabrication of Power TFT Devices and Electrical Characteristics)

  • 이우선;정용호;김남오
    • 한국전기전자재료학회논문지
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    • 제11권10호
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    • pp.790-795
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    • 1998
  • Fabrication of inverted staggered power TFT devices and electrical characteristic were investigated. 16 fingers with drain and source electrode of TFT and 100V output voltage were designed successfully. It is observed that as $V_g$ increased, $I_d$ increase exponentially. Because of localized deep states of a-Si, $I_d$ shows irregular variation at low voltage. Output and transfer characteristic showed the same as typical variation. But electrical characteristic strongly depend on the channel length and thickness of silicon nitride and amorphous silicon.

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SONOS 구조를 갖는 멀티 비트 소자의 프로그래밍 특성 (Programming Characteristics of the Multi-bit Devices Based on SONOS Structure)

  • 김주연
    • 한국전기전자재료학회논문지
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    • 제16권9호
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    • pp.771-774
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    • 2003
  • In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

Speckle Defect by Dark Leakage Current in Nitride Stringer at the Edge of Shallow Trench Isolation for CMOS Image Sensors

  • Jeong, Woo-Yang;Yi, Keun-Man
    • Transactions on Electrical and Electronic Materials
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    • 제10권6호
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    • pp.189-192
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    • 2009
  • The leakage current in a CMOS image sensor (CIS) can have various origins. Leakage current investigations have focused on such things as cobalt-salicide, source and drain scheme, and shallow trench isolation (STI) profile. However, there have been few papers examining the effects on leakage current of nitride stringers that are formed by gate sidewall etching. So this study reports the results of a series of experiments on the effects of a nitride stringer on real display images. Different step heights were fabricated during a STI chemical mechanical polishing process to form different nitride stringer sizes, arsenic and boron were implanted in each fabricated photodiode, and the doping density profiles were analyzed. Electrons that moved onto the silicon surface caused the dark leakage current, which in turn brought up the speckle defect on the display image in the CIS.

SOI MOSFET의 단채널 효과를 고려한 문턱전압과 I-V특성 연구 (A Study on Threshold Voltage and I-V Characteristics by considering the Short-Channel Effect of SOI MOSFET)

  • 김현철;나준호;김철성
    • 전자공학회논문지A
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    • 제31A권8호
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    • pp.34-45
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    • 1994
  • We studied threshold voltages and I-V characteristics. considering short channel effect of the fully depleted thin film n-channel SOI MOSFET. We presented a charge sharing model when the back surface of short channel shows accumulation depletion and inversion state respectively. A degree of charge sharing can be compared according to each of back-surface conditions. Mobility is not assumed as constant and besides bulk mobility both the mobility defined by acoustic phonon scattering and the mobility by surface roughness scattering are taken into consideration. I-V characteristics is then implemented by the mobility including vertical and parallel electric field. kThe validity of the model is proved with the 2-dimensional device simulation (MEDICI) and experimental results. The threshold voltage and charge sharing region controlled by source or drain reduced with increasing back gate voltage. The mobility is dependent upon scattering effect and electric field. so it has a strong influence on I-V characteristics.

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