• Journal of Navigation and Port Research
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• v.27 no.2
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• pp.233-238
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• 2003

Due to the impermeability of outer wall facilities such as Breakwaters which dissipates the wave energy and keeps harbor tranquility, the enclosed area of harbor becomes partially blocked and the water exchange can be reduced. Recent trends of port development protect water quality and emphasize Water-Front, so the method which enhances the circulation of harbor waters and the dilution of the water pollutants are studied. The best improvement of water quality is a remove of pollutant source on land, but an enclosed port must be enhanced the tidal exchange. For this end, the best improvement may be made a drain-route on the existing outer wall facilities. In this study, the numerical computations were carried out to predict the circulation of harbor waters and the tidal exchange through the drain-rout in the polluted harbor(Samchonpo-guhang) located at the east coast of South Sea. Computational models adopting FDM(Finite Difference Method) were used here and were already verified from the previous studies und ocean survey. As a result of this study, circulation and the tidal exchange at the harbor before and after introduction of drain-route were assessed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.57-63
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• 2008

In this paper, the dependence of MOSFET performance on the channel stress is characterized in depth. The tensile and compressive stresses are applied to CMOSFET using a nitride film which is used for the contact etch stop layer (CESL). Drain current of NMOS and PMOS is increased by inducing tensile and compressive stress, respectively, due to the increased mobility as well known. In case of NMOS with tensile stress, both decrease of the back scattering ratio ($\tau_{sat}$) and increase of the thermal injection velocity ($V_{inj}$) contribute the increase of mobility. It is also shown that the decrease of the $\tau_{sat}$ is due to the decrease of the mean free path ($\lambda_O$). On the other hand, the mobility improvement of PMOS with compressive stress is analyzed to be only due to the so increased $V_{inj}$ because the back scattering ratio is increased by the compressive stress. Therefore it was confirmed that the device performance has a strong dependency on the channel back scattering of the inversion layer and thermal injection velocity at the source side and NMOS and PMOS have different dependency on them.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.572-578
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• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.727-729
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• 2008

Organic field-effort transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1671-1673
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• 1999

일반적으로 SOI 소자에 대한 연구는 film 두께. 채널길이 그리고 doping 농도에 따라 폭넓게 연구되어 왔다. 제안한 소스/드레인 비대칭 SOI 소자는 일반적인 LDD SOI 소자와 비교하여 항복전압은 거의 비슷한 반면. 전류 구동능력은 훨씬향상된 소자를 구현 시킬수 있었다. 비대칭 SOI 소자를 설계하기 위하여 최적화된 공정조건을 모의 실험용 TCAD Simulator (SILVACO)를 이용하여 검증하였다. 검증된 공정 변수를 이용하여 모의 실험을 해보았더니 항복전압과 전류 구동능력에서 좋은 특성을 나타내었다.

• Journal of Information Display
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• v.13 no.2
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.455-459
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• 2004

Electrostatic discharge(ESD) is a serious reliability concern. It causes approximately most of all field failures of integrated circuits. Inevitably, future IC technologies will shrink the dimensions of interconnects, gate oxides, and junction depths, causing ICs to be increasingly susceptible to ESD-induced damage [1][2][3]. This thesis shows the optimization of the ESD protection circuit based on the tested results of MM (Machine Model) and HBM (Human Body Model), regardless of existing Reference in fully silicided 0.18 um CMOS process. His thesis found that, by the formation of silicide in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness [8].

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.787-791
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• 2004

We investigated field-effect ion-transport devices based on carbon nanotubes by using classical molecular dynamics simulations under applied external force fields, and we present model schematics that car be applied to the nanoscale data storage devices and unipolar ionic field-effect transistors. As the applied external force field is increased, potassium ions rapidly flow through the nanochannel. Under low external force fields, ther nal fluctuations of the nanochannels affect tunneling of the potassium ions whereas the effects of thermal fluctuations are negligible under high external force fields. Since the electric current conductivity increases when potassium ions are inserted into fullerenes or carbon nanotubes, the field effect due to the gate, which can modify the position of the potassium ions, changes the tunneling current between the drain and the source.