• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.546-549
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• 2009

In this paper, we investigated the effects of different source/drain (S/D) electrode materials in thin film transistors (TFTs) based on indium-gallium-zinc oxide (IGZO) semiconductor. A transfer length and effective resistances between S/D electrodes and amorphous IGZO thin-film transistors were examined. Intrinsic TFT parameters were extracted by the transmission line method (TLM) using a series of TFTs with different channel lengths measured at a low drain voltage. The TFTs fabricated with Cu S/D electrodes showed the lowest contact resistance and transfer length indicating good ohmic characteristics, and good transfer characteristics with a field-effect mobility (${\mu}_{FE}$) of 10.0 $cm^2$/Vs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• Journal of Semiconductor Engineering
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• v.3 no.2
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• pp.161-167
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• 2022

Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• Proceedings of the Korea Water Resources Association Conference
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• 2021.06a
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• pp.146-146
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• 2021

A contamination event occurring in water distribution networks (WDNs) needs to be handled with the appropriate mitigation strategy to protect public health safety and ensure water supply service continuation. Typically the mitigation phase consists of contaminant sensing, public warning, network inspection, and recovery. After the contaminant source has been detected and treated, contaminants still exist in the network, and the contaminated water should be flushed out. The recovery period is critical to remove any lingering contaminant in a rapid and non-detrimental manner. The contaminant flushing can be done in several ways. Conventionally, the opening of hydrants is applied to drain the contaminant out of the system. Relying on advanced information and communication technology (ICT) on WDN management, warning and information can be distributed fast through electronic media. Water utilities can inform their customers to participate in the contaminant flushing by opening and closing their house faucets to drain the contaminated water. The household draining strategy consists of determining sectors and timeslots of the WDN users based on hydraulic simulation. The number of sectors should be controlled to maintain sufficient pressure for faucet draining. The draining timeslot is determined through hydraulic simulation to identify the draining time required for each sector. The effectiveness of the strategy is evaluated using three measurements, such as Wasted Water (WW), Flushing Duration (FD), and Pipe Erosion (PE). The optimal draining strategy (i.e., group and timeslot allocation) in the WDN can be determined by minimizing the measures.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.65-73
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• 1986

Experiment have been conducted about thin oxide characteristics according to O2/N2 ratio needed for EEPROM cell fabrication. As a result, we think that there is no problem even if we grow oxide layer with large O2/N2 ratio and short exidation time and when the water is implated by As before oxidation, the oxide breakdown field is about IMV/cm lower than that is not implanted. Especially, the thin oxide characteristic seems to be affected largely by wafer cleaning and oxidation in air. On the basis of these, tunnel type EEPROM cell is fabricated by 3um CMOS process and its characteristic is studied. Tunnel oxide thickness(100\ulcorner is chosen to allow Fowler-Nordheim tunneling to charge the floating gate at the desired programming voltage and tunnel area(2x2um\ulcorneris chosen to increase capacitive coupling ratio. For program operation, high voltage (20-22V) is applied to the control gate, while both drain and source are gdrounded. The drain voltage for erase is 16V. It is shown that charge retention characteristics is not limited by leakage in the oxide and program/erase endurance is over 10E4 cycles of program erase operation.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Proceedings of the Korean Nuclear Society Conference
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• 2004.10a
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• pp.719-720
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• 2004

A multi-megawatt long pulse ion source (LPIS) of neutral beam injector was developed for the KSTAR. Beam extraction experiments of the LPIS were carried out at the neutral beam test stand (NBTS). Design requirements for the ion source were 120 kV/65 A deuterium beam and a 300 s pulse length. A maximum ion density of $9.1310^{11}$ $cm^{-3}$ was measured by using electric probes, and an optimum arc efficiency of 0.46 A/kW was estimated with ion saturation current of the probes, arc power, and total beam area. An arcing problem, caused by the structural defect of decelerating grid supporter, in the third gap was solved by the blocking of backstream ion particles, originated from the plasma in the neutralizer duct, through the unnecessary spaces on the side of grid supporter. A maximum drain power of 1.5 MW (i.e. 70 kV/21 A) with hydrogen was measured for a pulse duration of 0.5 s. Optimum beam perveance was ranged from 0.75 to 0.85. An improved design of accelerator for the effective control of beam particle trajectory should provide higher beam perveance.

• East Asian Economic Review
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• v.20 no.2
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• pp.229-275
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• 2016

We study the effect of the high-skilled emigration rate on the growth rate of the source countries. We incorporate the foreign direct investment and the policy variables into the panel model and also their interactions with the high-skilled emigration rate, as they are related to the network externality that may be created by the high-skilled emigrants working abroad. We apply the static fixed-effects model and compare it with the results obtained in the dynamic panel model with system generalized methods of moments estimators. We find the negative effect of the high-skilled emigration rate by itself and in its interaction with the foreign direct investment only in the dynamic model. However, we find positive coefficient for the interaction of the high-skilled emigration rate and the civil liberties index, which holds across the static and dynamic specifications. This implies that the effect of the high-skilled emigration rate on the growth rate of the source countries can be positive, and the extent is larger for countries with 'poor' civil liberties. The developing countries with low levels of foreign direct investment inflows and 'poor' civil liberties can best benefit from the high levels of skilled emigration outward. Through finding significant interactions with other variables, we confirm that the high-skilled emigration should be considered along with other related variables in measuring its impact on growth. The implications offer suggestions for the international trade and aid policies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.66-74
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• 2012

In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.39-48
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• 2016

In this paper, we propose thermal resistance compact model of FinFET structure that has hexagon shaped source/drain. The heating effect and thermal properties were increased by reduced size of the device, and thermal resistance is an important factor to analyze the effect and the properties. The heat source and each contact that is moved heat out were set up in transistor, and domain is divided by the heat source and the four parts of contacts : source, drain, gate, substrate. Each contact thermal resistance model is subdivided as a easily interpretable structure by analyzing the temperature and heat flow of the TCAD simulation results. The domains are modeled based on an integration or conformal mapping method through the structure parameters according to its structure. First modeled by analyzing the thermal resistance to a single fin, and applying the change in the parameter of the channel increases to improve the accuracy of the thermal resistance model of the multi-fin/ finger. The proposed thermal resistance model was compared to the thermal resistance by analyzing results of the 3D Technology CAD simulations, and the proposed total thermal resistance model has an error of 3 % less in single and multi-finl. The proposed thermal resistance model can predict the thermal resistance due to the increase of the fin / finger, and the circuit characteristics can be improved by calculating the self-heating effect and thermal characterization.